ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
   4 # Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
   5 # Copyright (c) 2016, Linaro Limited. All rights reserved.
   6 #
   7 # This program and the accompanying materials
   8 # are licensed and made available under the terms and conditions of the BSD License
   9 # which accompanies this distribution.  The full text of the license may be found at
  10 # http://opensource.org/licenses/bsd-license.php
  11 #
  12 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  13 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  14 #
  15 #------------------------------------------------------------------------------
  16
  17 #include <AsmMacroIoLib.h>
  18
  19 .set DC_ON, (0x1<<2)
  20 .set IC_ON, (0x1<<12)
  21 .set CTRL_M_BIT,  (1 << 0)
  22 .set CTRL_C_BIT,  (1 << 2)
  23 .set CTRL_B_BIT,  (1 << 7)
  24 .set CTRL_I_BIT,  (1 << 12)
  25
  26
  27 ASM_FUNC(ArmInvalidateDataCacheEntryByMVA)
  28   mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line
  29   bx      lr
  30
  31 ASM_FUNC(ArmCleanDataCacheEntryByMVA)
  32   mcr     p15, 0, r0, c7, c10, 1  @clean single data cache line
  33   bx      lr
  34
  35
  36 ASM_FUNC(ArmCleanDataCacheEntryToPoUByMVA)
  37   mcr     p15, 0, r0, c7, c11, 1  @clean single data cache line to PoU
  38   bx      lr
  39
  40 ASM_FUNC(ArmInvalidateInstructionCacheEntryToPoUByMVA)
  41   mcr     p15, 0, r0, c7, c5, 1  @Invalidate single instruction cache line to PoU
  42   mcr     p15, 0, r0, c7, c5, 7  @Invalidate branch predictor
  43   bx      lr
  44
  45 ASM_FUNC(ArmCleanInvalidateDataCacheEntryByMVA)
  46   mcr     p15, 0, r0, c7, c14, 1  @clean and invalidate single data cache line
  47   bx      lr
  48
  49
  50 ASM_FUNC(ArmInvalidateDataCacheEntryBySetWay)
  51   mcr     p15, 0, r0, c7, c6, 2        @ Invalidate this line
  52   bx      lr
  53
  54
  55 ASM_FUNC(ArmCleanInvalidateDataCacheEntryBySetWay)
  56   mcr     p15, 0, r0, c7, c14, 2       @ Clean and Invalidate this line
  57   bx      lr
  58
  59
  60 ASM_FUNC(ArmCleanDataCacheEntryBySetWay)
  61   mcr     p15, 0, r0, c7, c10, 2       @ Clean this line
  62   bx      lr
  63
  64 ASM_FUNC(ArmInvalidateInstructionCache)
  65   mcr     p15,0,R0,c7,c5,0      @Invalidate entire instruction cache
  66   dsb
  67   isb
  68   bx      LR
  69
  70 ASM_FUNC(ArmEnableMmu)
  71   mrc     p15,0,R0,c1,c0,0
  72   orr     R0,R0,#1
  73   mcr     p15,0,R0,c1,c0,0
  74   dsb
  75   isb
  76   bx      LR
  77
  78
  79 ASM_FUNC(ArmDisableMmu)
  80   mrc     p15,0,R0,c1,c0,0
  81   bic     R0,R0,#1
  82   mcr     p15,0,R0,c1,c0,0      @Disable MMU
  83
  84   mcr     p15,0,R0,c8,c7,0      @Invalidate TLB
  85   mcr     p15,0,R0,c7,c5,6      @Invalidate Branch predictor array
  86   dsb
  87   isb
  88   bx      LR
  89
  90 ASM_FUNC(ArmDisableCachesAndMmu)
  91   mrc   p15, 0, r0, c1, c0, 0           @ Get control register
  92   bic   r0, r0, #CTRL_M_BIT             @ Disable MMU
  93   bic   r0, r0, #CTRL_C_BIT             @ Disable D Cache
  94   bic   r0, r0, #CTRL_I_BIT             @ Disable I Cache
  95   mcr   p15, 0, r0, c1, c0, 0           @ Write control register
  96   dsb
  97   isb
  98   bx      LR
  99
 100 ASM_FUNC(ArmMmuEnabled)
 101   mrc     p15,0,R0,c1,c0,0
 102   and     R0,R0,#1
 103   bx      LR
 104
 105 ASM_FUNC(ArmEnableDataCache)
 106   ldr     R1,=DC_ON
 107   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 108   orr     R0,R0,R1              @Set C bit
 109   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 110   dsb
 111   isb
 112   bx      LR
 113
 114 ASM_FUNC(ArmDisableDataCache)
 115   ldr     R1,=DC_ON
 116   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 117   bic     R0,R0,R1              @Clear C bit
 118   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 119   dsb
 120   isb
 121   bx      LR
 122
 123 ASM_FUNC(ArmEnableInstructionCache)
 124   ldr     R1,=IC_ON
 125   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 126   orr     R0,R0,R1              @Set I bit
 127   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 128   dsb
 129   isb
 130   bx      LR
 131
 132 ASM_FUNC(ArmDisableInstructionCache)
 133   ldr     R1,=IC_ON
 134   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 135   bic     R0,R0,R1              @Clear I bit.
 136   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 137   dsb
 138   isb
 139   bx      LR
 140
 141 ASM_FUNC(ArmEnableSWPInstruction)
 142   mrc     p15, 0, r0, c1, c0, 0
 143   orr     r0, r0, #0x00000400
 144   mcr     p15, 0, r0, c1, c0, 0
 145   isb
 146   bx      LR
 147
 148 ASM_FUNC(ArmEnableBranchPrediction)
 149   mrc     p15, 0, r0, c1, c0, 0
 150   orr     r0, r0, #0x00000800
 151   mcr     p15, 0, r0, c1, c0, 0
 152   dsb
 153   isb
 154   bx      LR
 155
 156 ASM_FUNC(ArmDisableBranchPrediction)
 157   mrc     p15, 0, r0, c1, c0, 0
 158   bic     r0, r0, #0x00000800
 159   mcr     p15, 0, r0, c1, c0, 0
 160   dsb
 161   isb
 162   bx      LR
 163
 164 ASM_FUNC(ArmSetLowVectors)
 165   mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
 166   bic     r0, r0, #0x00002000   @ clear V bit
 167   mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
 168   isb
 169   bx      LR
 170
 171 ASM_FUNC(ArmSetHighVectors)
 172   mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
 173   orr     r0, r0, #0x00002000   @ Set V bit
 174   mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
 175   isb
 176   bx      LR
 177
 178 ASM_FUNC(ArmV7AllDataCachesOperation)
 179   stmfd SP!,{r4-r12, LR}
 180   mov   R1, R0                @ Save Function call in R1
 181   mrc   p15, 1, R6, c0, c0, 1 @ Read CLIDR
 182   ands  R3, R6, #0x7000000    @ Mask out all but Level of Coherency (LoC)
 183   mov   R3, R3, LSR #23       @ Cache level value (naturally aligned)
 184   beq   L_Finished
 185   mov   R10, #0
 186
 187 Loop1:
 188   add   R2, R10, R10, LSR #1  @ Work out 3xcachelevel
 189   mov   R12, R6, LSR R2       @ bottom 3 bits are the Cache type for this level
 190   and   R12, R12, #7          @ get those 3 bits alone
 191   cmp   R12, #2
 192   blt   L_Skip                  @ no cache or only instruction cache at this level
 193   mcr   p15, 2, R10, c0, c0, 0  @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
 194   isb                           @ isb to sync the change to the CacheSizeID reg
 195   mrc   p15, 1, R12, c0, c0, 0  @ reads current Cache Size ID register (CCSIDR)
 196   and   R2, R12, #0x7           @ extract the line length field
 197   add   R2, R2, #4              @ add 4 for the line length offset (log2 16 bytes)
 198 @  ldr   R4, =0x3FF
 199   mov   R4, #0x400
 200   sub   R4, R4, #1
 201   ands  R4, R4, R12, LSR #3     @ R4 is the max number on the way size (right aligned)
 202   clz   R5, R4                  @ R5 is the bit position of the way size increment
 203 @  ldr   R7, =0x00007FFF
 204   mov   R7, #0x00008000
 205   sub   R7, R7, #1
 206   ands  R7, R7, R12, LSR #13    @ R7 is the max number of the index size (right aligned)
 207
 208 Loop2:
 209   mov   R9, R4                  @ R9 working copy of the max way size (right aligned)
 210
 211 Loop3:
 212   orr   R0, R10, R9, LSL R5     @ factor in the way number and cache number into R11
 213   orr   R0, R0, R7, LSL R2      @ factor in the index number
 214
 215   blx   R1
 216
 217   subs  R9, R9, #1              @ decrement the way number
 218   bge   Loop3
 219   subs  R7, R7, #1              @ decrement the index
 220   bge   Loop2
 221 L_Skip:
 222   add   R10, R10, #2            @ increment the cache number
 223   cmp   R3, R10
 224   bgt   Loop1
 225
 226 L_Finished:
 227   dsb
 228   ldmfd SP!, {r4-r12, lr}
 229   bx    LR
 230
 231 ASM_FUNC(ArmDataMemoryBarrier)
 232   dmb
 233   bx      LR
 234
 235 ASM_FUNC(ArmDataSynchronizationBarrier)
 236   dsb
 237   bx      LR
 238
 239 ASM_FUNC(ArmInstructionSynchronizationBarrier)
 240   isb
 241   bx      LR
 242
 243 ASM_FUNC(ArmReadVBar)
 244   # Set the Address of the Vector Table in the VBAR register
 245   mrc     p15, 0, r0, c12, c0, 0
 246   bx      lr
 247
 248 ASM_FUNC(ArmWriteVBar)
 249   # Set the Address of the Vector Table in the VBAR register
 250   mcr     p15, 0, r0, c12, c0, 0
 251   # Ensure the SCTLR.V bit is clear
 252   mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
 253   bic     r0, r0, #0x00002000   @ clear V bit
 254   mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
 255   isb
 256   bx      lr
 257
 258 ASM_FUNC(ArmEnableVFP)
 259   # Read CPACR (Coprocessor Access Control Register)
 260   mrc     p15, 0, r0, c1, c0, 2
 261   # Enable VPF access (Full Access to CP10, CP11) (V* instructions)
 262   orr     r0, r0, #0x00f00000
 263   # Write back CPACR (Coprocessor Access Control Register)
 264   mcr     p15, 0, r0, c1, c0, 2
 265   isb
 266   # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
 267   mov     r0, #0x40000000
 268 #ifndef __clang__
 269   mcr     p10,#0x7,r0,c8,c0,#0
 270 #else
 271   vmsr    fpexc, r0
 272 #endif
 273   bx      lr
 274
 275 ASM_FUNC(ArmCallWFI)
 276   wfi
 277   bx      lr
 278
 279 #Note: Return 0 in Uniprocessor implementation
 280 ASM_FUNC(ArmReadCbar)
 281   mrc     p15, 4, r0, c15, c0, 0  @ Read Configuration Base Address Register
 282   bx      lr
 283
 284 ASM_FUNC(ArmReadMpidr)
 285   mrc     p15, 0, r0, c0, c0, 5       @ read MPIDR
 286   bx      lr
 287
 288 ASM_FUNC(ArmReadTpidrurw)
 289   mrc     p15, 0, r0, c13, c0, 2    @ read TPIDRURW
 290   bx      lr
 291
 292 ASM_FUNC(ArmWriteTpidrurw)
 293   mcr     p15, 0, r0, c13, c0, 2    @ write TPIDRURW
 294   bx      lr
 295
 296 ASM_FUNC(ArmIsArchTimerImplemented)
 297   mrc    p15, 0, r0, c0, c1, 1     @ Read ID_PFR1
 298   and    r0, r0, #0x000F0000
 299   bx     lr
 300
 301 ASM_FUNC(ArmReadIdPfr1)
 302   mrc    p15, 0, r0, c0, c1, 1     @ Read ID_PFR1 Register
 303   bx     lr
 304
 305 ASM_FUNCTION_REMOVE_IF_UNREFERENCED