ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
   4 # Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
   5 #
   6 # This program and the accompanying materials
   7 # are licensed and made available under the terms and conditions of the BSD License
   8 # which accompanies this distribution.  The full text of the license may be found at
   9 # http://opensource.org/licenses/bsd-license.php
  10 #
  11 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 #
  14 #------------------------------------------------------------------------------
  15
  16 .text
  17 .align 2
  18
  19 GCC_ASM_EXPORT (ArmInvalidateInstructionCache)
  20 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)
  21 GCC_ASM_EXPORT (ArmInvalidateInstructionCacheEntryToPoUByMVA)
  22 GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)
  23 GCC_ASM_EXPORT (ArmCleanDataCacheEntryToPoUByMVA)
  24 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)
  25 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)
  26 GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)
  27 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay)
  28 GCC_ASM_EXPORT (ArmEnableMmu)
  29 GCC_ASM_EXPORT (ArmDisableMmu)
  30 GCC_ASM_EXPORT (ArmDisableCachesAndMmu)
  31 GCC_ASM_EXPORT (ArmMmuEnabled)
  32 GCC_ASM_EXPORT (ArmEnableDataCache)
  33 GCC_ASM_EXPORT (ArmDisableDataCache)
  34 GCC_ASM_EXPORT (ArmEnableInstructionCache)
  35 GCC_ASM_EXPORT (ArmDisableInstructionCache)
  36 GCC_ASM_EXPORT (ArmEnableSWPInstruction)
  37 GCC_ASM_EXPORT (ArmEnableBranchPrediction)
  38 GCC_ASM_EXPORT (ArmDisableBranchPrediction)
  39 GCC_ASM_EXPORT (ArmSetLowVectors)
  40 GCC_ASM_EXPORT (ArmSetHighVectors)
  41 GCC_ASM_EXPORT (ArmV7AllDataCachesOperation)
  42 GCC_ASM_EXPORT (ArmDataMemoryBarrier)
  43 GCC_ASM_EXPORT (ArmDataSynchronizationBarrier)
  44 GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)
  45 GCC_ASM_EXPORT (ArmReadVBar)
  46 GCC_ASM_EXPORT (ArmWriteVBar)
  47 GCC_ASM_EXPORT (ArmEnableVFP)
  48 GCC_ASM_EXPORT (ArmCallWFI)
  49 GCC_ASM_EXPORT (ArmReadCbar)
  50 GCC_ASM_EXPORT (ArmReadMpidr)
  51 GCC_ASM_EXPORT (ArmReadTpidrurw)
  52 GCC_ASM_EXPORT (ArmWriteTpidrurw)
  53 GCC_ASM_EXPORT (ArmIsArchTimerImplemented)
  54 GCC_ASM_EXPORT (ArmReadIdPfr1)
  55
  56 .set DC_ON, (0x1<<2)
  57 .set IC_ON, (0x1<<12)
  58 .set CTRL_M_BIT,  (1 << 0)
  59 .set CTRL_C_BIT,  (1 << 2)
  60 .set CTRL_B_BIT,  (1 << 7)
  61 .set CTRL_I_BIT,  (1 << 12)
  62
  63
  64 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
  65   mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line
  66   bx      lr
  67
  68 ASM_PFX(ArmCleanDataCacheEntryByMVA):
  69   mcr     p15, 0, r0, c7, c10, 1  @clean single data cache line
  70   bx      lr
  71
  72
  73 ASM_PFX(ArmCleanDataCacheEntryToPoUByMVA):
  74   mcr     p15, 0, r0, c7, c11, 1  @clean single data cache line to PoU
  75   bx      lr
  76
  77 ASM_PFX(ArmInvalidateInstructionCacheEntryToPoUByMVA):
  78   mcr     p15, 0, r0, c7, c5, 1  @Invalidate single instruction cache line to PoU
  79   mcr     p15, 0, r0, c7, c5, 7  @Invalidate branch predictor
  80   bx      lr
  81
  82 ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
  83   mcr     p15, 0, r0, c7, c14, 1  @clean and invalidate single data cache line
  84   bx      lr
  85
  86
  87 ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
  88   mcr     p15, 0, r0, c7, c6, 2        @ Invalidate this line
  89   bx      lr
  90
  91
  92 ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
  93   mcr     p15, 0, r0, c7, c14, 2       @ Clean and Invalidate this line
  94   bx      lr
  95
  96
  97 ASM_PFX(ArmCleanDataCacheEntryBySetWay):
  98   mcr     p15, 0, r0, c7, c10, 2       @ Clean this line
  99   bx      lr
 100
 101 ASM_PFX(ArmInvalidateInstructionCache):
 102   mcr     p15,0,R0,c7,c5,0      @Invalidate entire instruction cache
 103   dsb
 104   isb
 105   bx      LR
 106
 107 ASM_PFX(ArmEnableMmu):
 108   mrc     p15,0,R0,c1,c0,0
 109   orr     R0,R0,#1
 110   mcr     p15,0,R0,c1,c0,0
 111   dsb
 112   isb
 113   bx      LR
 114
 115
 116 ASM_PFX(ArmDisableMmu):
 117   mrc     p15,0,R0,c1,c0,0
 118   bic     R0,R0,#1
 119   mcr     p15,0,R0,c1,c0,0      @Disable MMU
 120
 121   mcr     p15,0,R0,c8,c7,0      @Invalidate TLB
 122   mcr     p15,0,R0,c7,c5,6      @Invalidate Branch predictor array
 123   dsb
 124   isb
 125   bx      LR
 126
 127 ASM_PFX(ArmDisableCachesAndMmu):
 128   mrc   p15, 0, r0, c1, c0, 0           @ Get control register
 129   bic   r0, r0, #CTRL_M_BIT             @ Disable MMU
 130   bic   r0, r0, #CTRL_C_BIT             @ Disable D Cache
 131   bic   r0, r0, #CTRL_I_BIT             @ Disable I Cache
 132   mcr   p15, 0, r0, c1, c0, 0           @ Write control register
 133   dsb
 134   isb
 135   bx      LR
 136
 137 ASM_PFX(ArmMmuEnabled):
 138   mrc     p15,0,R0,c1,c0,0
 139   and     R0,R0,#1
 140   bx      LR
 141
 142 ASM_PFX(ArmEnableDataCache):
 143   ldr     R1,=DC_ON
 144   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 145   orr     R0,R0,R1              @Set C bit
 146   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 147   dsb
 148   isb
 149   bx      LR
 150
 151 ASM_PFX(ArmDisableDataCache):
 152   ldr     R1,=DC_ON
 153   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 154   bic     R0,R0,R1              @Clear C bit
 155   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 156   dsb
 157   isb
 158   bx      LR
 159
 160 ASM_PFX(ArmEnableInstructionCache):
 161   ldr     R1,=IC_ON
 162   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 163   orr     R0,R0,R1              @Set I bit
 164   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 165   dsb
 166   isb
 167   bx      LR
 168
 169 ASM_PFX(ArmDisableInstructionCache):
 170   ldr     R1,=IC_ON
 171   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 172   bic     R0,R0,R1              @Clear I bit.
 173   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 174   dsb
 175   isb
 176   bx      LR
 177
 178 ASM_PFX(ArmEnableSWPInstruction):
 179   mrc     p15, 0, r0, c1, c0, 0
 180   orr     r0, r0, #0x00000400
 181   mcr     p15, 0, r0, c1, c0, 0
 182   isb
 183   bx      LR
 184
 185 ASM_PFX(ArmEnableBranchPrediction):
 186   mrc     p15, 0, r0, c1, c0, 0
 187   orr     r0, r0, #0x00000800
 188   mcr     p15, 0, r0, c1, c0, 0
 189   dsb
 190   isb
 191   bx      LR
 192
 193 ASM_PFX(ArmDisableBranchPrediction):
 194   mrc     p15, 0, r0, c1, c0, 0
 195   bic     r0, r0, #0x00000800
 196   mcr     p15, 0, r0, c1, c0, 0
 197   dsb
 198   isb
 199   bx      LR
 200
 201 ASM_PFX(ArmSetLowVectors):
 202   mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
 203   bic     r0, r0, #0x00002000   @ clear V bit
 204   mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
 205   isb
 206   bx      LR
 207
 208 ASM_PFX(ArmSetHighVectors):
 209   mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
 210   orr     r0, r0, #0x00002000   @ Set V bit
 211   mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
 212   isb
 213   bx      LR
 214
 215 ASM_PFX(ArmV7AllDataCachesOperation):
 216   stmfd SP!,{r4-r12, LR}
 217   mov   R1, R0                @ Save Function call in R1
 218   mrc   p15, 1, R6, c0, c0, 1 @ Read CLIDR
 219   ands  R3, R6, #0x7000000    @ Mask out all but Level of Coherency (LoC)
 220   mov   R3, R3, LSR #23       @ Cache level value (naturally aligned)
 221   beq   L_Finished
 222   mov   R10, #0
 223
 224 Loop1:
 225   add   R2, R10, R10, LSR #1  @ Work out 3xcachelevel
 226   mov   R12, R6, LSR R2       @ bottom 3 bits are the Cache type for this level
 227   and   R12, R12, #7          @ get those 3 bits alone
 228   cmp   R12, #2
 229   blt   L_Skip                  @ no cache or only instruction cache at this level
 230   mcr   p15, 2, R10, c0, c0, 0  @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
 231   isb                           @ isb to sync the change to the CacheSizeID reg
 232   mrc   p15, 1, R12, c0, c0, 0  @ reads current Cache Size ID register (CCSIDR)
 233   and   R2, R12, #0x7           @ extract the line length field
 234   add   R2, R2, #4              @ add 4 for the line length offset (log2 16 bytes)
 235 @  ldr   R4, =0x3FF
 236   mov   R4, #0x400
 237   sub   R4, R4, #1
 238   ands  R4, R4, R12, LSR #3     @ R4 is the max number on the way size (right aligned)
 239   clz   R5, R4                  @ R5 is the bit position of the way size increment
 240 @  ldr   R7, =0x00007FFF
 241   mov   R7, #0x00008000
 242   sub   R7, R7, #1
 243   ands  R7, R7, R12, LSR #13    @ R7 is the max number of the index size (right aligned)
 244
 245 Loop2:
 246   mov   R9, R4                  @ R9 working copy of the max way size (right aligned)
 247
 248 Loop3:
 249   orr   R0, R10, R9, LSL R5     @ factor in the way number and cache number into R11
 250   orr   R0, R0, R7, LSL R2      @ factor in the index number
 251
 252   blx   R1
 253
 254   subs  R9, R9, #1              @ decrement the way number
 255   bge   Loop3
 256   subs  R7, R7, #1              @ decrement the index
 257   bge   Loop2
 258 L_Skip:
 259   add   R10, R10, #2            @ increment the cache number
 260   cmp   R3, R10
 261   bgt   Loop1
 262
 263 L_Finished:
 264   dsb
 265   ldmfd SP!, {r4-r12, lr}
 266   bx    LR
 267
 268 ASM_PFX(ArmDataMemoryBarrier):
 269   dmb
 270   bx      LR
 271
 272 ASM_PFX(ArmDataSynchronizationBarrier):
 273   dsb
 274   bx      LR
 275
 276 ASM_PFX(ArmInstructionSynchronizationBarrier):
 277   isb
 278   bx      LR
 279
 280 ASM_PFX(ArmReadVBar):
 281   # Set the Address of the Vector Table in the VBAR register
 282   mrc     p15, 0, r0, c12, c0, 0
 283   bx      lr
 284
 285 ASM_PFX(ArmWriteVBar):
 286   # Set the Address of the Vector Table in the VBAR register
 287   mcr     p15, 0, r0, c12, c0, 0
 288   # Ensure the SCTLR.V bit is clear
 289   mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
 290   bic     r0, r0, #0x00002000   @ clear V bit
 291   mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
 292   isb
 293   bx      lr
 294
 295 ASM_PFX(ArmEnableVFP):
 296   # Read CPACR (Coprocessor Access Control Register)
 297   mrc     p15, 0, r0, c1, c0, 2
 298   # Enable VPF access (Full Access to CP10, CP11) (V* instructions)
 299   orr     r0, r0, #0x00f00000
 300   # Write back CPACR (Coprocessor Access Control Register)
 301   mcr     p15, 0, r0, c1, c0, 2
 302   isb
 303   # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
 304   mov     r0, #0x40000000
 305 #ifndef __clang__
 306   mcr     p10,#0x7,r0,c8,c0,#0
 307 #else
 308   vmsr    fpexc, r0
 309 #endif
 310   bx      lr
 311
 312 ASM_PFX(ArmCallWFI):
 313   wfi
 314   bx      lr
 315
 316 #Note: Return 0 in Uniprocessor implementation
 317 ASM_PFX(ArmReadCbar):
 318   mrc     p15, 4, r0, c15, c0, 0  @ Read Configuration Base Address Register
 319   bx      lr
 320
 321 ASM_PFX(ArmReadMpidr):
 322   mrc     p15, 0, r0, c0, c0, 5       @ read MPIDR
 323   bx      lr
 324
 325 ASM_PFX(ArmReadTpidrurw):
 326   mrc     p15, 0, r0, c13, c0, 2    @ read TPIDRURW
 327   bx      lr
 328
 329 ASM_PFX(ArmWriteTpidrurw):
 330   mcr     p15, 0, r0, c13, c0, 2    @ write TPIDRURW
 331   bx      lr
 332
 333 ASM_PFX(ArmIsArchTimerImplemented):
 334   mrc    p15, 0, r0, c0, c1, 1     @ Read ID_PFR1
 335   and    r0, r0, #0x000F0000
 336   bx     lr
 337
 338 ASM_PFX(ArmReadIdPfr1):
 339   mrc    p15, 0, r0, c0, c1, 1     @ Read ID_PFR1 Register
 340   bx     lr
 341
 342 ASM_FUNCTION_REMOVE_IF_UNREFERENCED