ArmPkg: ArmLib: purge incorrect ArmDrainWriteBuffer () alias
[mirror_edk2.git] / ArmPkg / Library / ArmLib / ArmV7 / ArmV7Support.S
1 #------------------------------------------------------------------------------
2 #
3 # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
4 # Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
5 #
6 # This program and the accompanying materials
7 # are licensed and made available under the terms and conditions of the BSD License
8 # which accompanies this distribution. The full text of the license may be found at
9 # http://opensource.org/licenses/bsd-license.php
10 #
11 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 #
14 #------------------------------------------------------------------------------
15
16 .text
17 .align 2
18
19 GCC_ASM_EXPORT (ArmInvalidateInstructionCache)
20 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)
21 GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)
22 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)
23 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)
24 GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)
25 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay)
26 GCC_ASM_EXPORT (ArmEnableMmu)
27 GCC_ASM_EXPORT (ArmDisableMmu)
28 GCC_ASM_EXPORT (ArmDisableCachesAndMmu)
29 GCC_ASM_EXPORT (ArmMmuEnabled)
30 GCC_ASM_EXPORT (ArmEnableDataCache)
31 GCC_ASM_EXPORT (ArmDisableDataCache)
32 GCC_ASM_EXPORT (ArmEnableInstructionCache)
33 GCC_ASM_EXPORT (ArmDisableInstructionCache)
34 GCC_ASM_EXPORT (ArmEnableSWPInstruction)
35 GCC_ASM_EXPORT (ArmEnableBranchPrediction)
36 GCC_ASM_EXPORT (ArmDisableBranchPrediction)
37 GCC_ASM_EXPORT (ArmSetLowVectors)
38 GCC_ASM_EXPORT (ArmSetHighVectors)
39 GCC_ASM_EXPORT (ArmV7AllDataCachesOperation)
40 GCC_ASM_EXPORT (ArmDataMemoryBarrier)
41 GCC_ASM_EXPORT (ArmDataSynchronizationBarrier)
42 GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)
43 GCC_ASM_EXPORT (ArmReadVBar)
44 GCC_ASM_EXPORT (ArmWriteVBar)
45 GCC_ASM_EXPORT (ArmEnableVFP)
46 GCC_ASM_EXPORT (ArmCallWFI)
47 GCC_ASM_EXPORT (ArmReadCbar)
48 GCC_ASM_EXPORT (ArmReadMpidr)
49 GCC_ASM_EXPORT (ArmReadTpidrurw)
50 GCC_ASM_EXPORT (ArmWriteTpidrurw)
51 GCC_ASM_EXPORT (ArmIsArchTimerImplemented)
52 GCC_ASM_EXPORT (ArmReadIdPfr1)
53 GCC_ASM_EXPORT (ArmReadIdMmfr0)
54
55 .set DC_ON, (0x1<<2)
56 .set IC_ON, (0x1<<12)
57 .set CTRL_M_BIT, (1 << 0)
58 .set CTRL_C_BIT, (1 << 2)
59 .set CTRL_B_BIT, (1 << 7)
60 .set CTRL_I_BIT, (1 << 12)
61
62
63 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
64 mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
65 bx lr
66
67 ASM_PFX(ArmCleanDataCacheEntryByMVA):
68 mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
69 bx lr
70
71
72 ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
73 mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line
74 bx lr
75
76
77 ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
78 mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line
79 bx lr
80
81
82 ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
83 mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line
84 bx lr
85
86
87 ASM_PFX(ArmCleanDataCacheEntryBySetWay):
88 mcr p15, 0, r0, c7, c10, 2 @ Clean this line
89 bx lr
90
91 ASM_PFX(ArmInvalidateInstructionCache):
92 mcr p15,0,R0,c7,c5,0 @Invalidate entire instruction cache
93 dsb
94 isb
95 bx LR
96
97 ASM_PFX(ArmEnableMmu):
98 mrc p15,0,R0,c1,c0,0
99 orr R0,R0,#1
100 mcr p15,0,R0,c1,c0,0
101 dsb
102 isb
103 bx LR
104
105
106 ASM_PFX(ArmDisableMmu):
107 mrc p15,0,R0,c1,c0,0
108 bic R0,R0,#1
109 mcr p15,0,R0,c1,c0,0 @Disable MMU
110
111 mcr p15,0,R0,c8,c7,0 @Invalidate TLB
112 mcr p15,0,R0,c7,c5,6 @Invalidate Branch predictor array
113 dsb
114 isb
115 bx LR
116
117 ASM_PFX(ArmDisableCachesAndMmu):
118 mrc p15, 0, r0, c1, c0, 0 @ Get control register
119 bic r0, r0, #CTRL_M_BIT @ Disable MMU
120 bic r0, r0, #CTRL_C_BIT @ Disable D Cache
121 bic r0, r0, #CTRL_I_BIT @ Disable I Cache
122 mcr p15, 0, r0, c1, c0, 0 @ Write control register
123 dsb
124 isb
125 bx LR
126
127 ASM_PFX(ArmMmuEnabled):
128 mrc p15,0,R0,c1,c0,0
129 and R0,R0,#1
130 bx LR
131
132 ASM_PFX(ArmEnableDataCache):
133 ldr R1,=DC_ON
134 mrc p15,0,R0,c1,c0,0 @Read control register configuration data
135 orr R0,R0,R1 @Set C bit
136 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
137 dsb
138 isb
139 bx LR
140
141 ASM_PFX(ArmDisableDataCache):
142 ldr R1,=DC_ON
143 mrc p15,0,R0,c1,c0,0 @Read control register configuration data
144 bic R0,R0,R1 @Clear C bit
145 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
146 dsb
147 isb
148 bx LR
149
150 ASM_PFX(ArmEnableInstructionCache):
151 ldr R1,=IC_ON
152 mrc p15,0,R0,c1,c0,0 @Read control register configuration data
153 orr R0,R0,R1 @Set I bit
154 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
155 dsb
156 isb
157 bx LR
158
159 ASM_PFX(ArmDisableInstructionCache):
160 ldr R1,=IC_ON
161 mrc p15,0,R0,c1,c0,0 @Read control register configuration data
162 bic R0,R0,R1 @Clear I bit.
163 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
164 dsb
165 isb
166 bx LR
167
168 ASM_PFX(ArmEnableSWPInstruction):
169 mrc p15, 0, r0, c1, c0, 0
170 orr r0, r0, #0x00000400
171 mcr p15, 0, r0, c1, c0, 0
172 isb
173 bx LR
174
175 ASM_PFX(ArmEnableBranchPrediction):
176 mrc p15, 0, r0, c1, c0, 0
177 orr r0, r0, #0x00000800
178 mcr p15, 0, r0, c1, c0, 0
179 dsb
180 isb
181 bx LR
182
183 ASM_PFX(ArmDisableBranchPrediction):
184 mrc p15, 0, r0, c1, c0, 0
185 bic r0, r0, #0x00000800
186 mcr p15, 0, r0, c1, c0, 0
187 dsb
188 isb
189 bx LR
190
191 ASM_PFX(ArmSetLowVectors):
192 mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
193 bic r0, r0, #0x00002000 @ clear V bit
194 mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
195 isb
196 bx LR
197
198 ASM_PFX(ArmSetHighVectors):
199 mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
200 orr r0, r0, #0x00002000 @ Set V bit
201 mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
202 isb
203 bx LR
204
205 ASM_PFX(ArmV7AllDataCachesOperation):
206 stmfd SP!,{r4-r12, LR}
207 mov R1, R0 @ Save Function call in R1
208 mrc p15, 1, R6, c0, c0, 1 @ Read CLIDR
209 ands R3, R6, #0x7000000 @ Mask out all but Level of Coherency (LoC)
210 mov R3, R3, LSR #23 @ Cache level value (naturally aligned)
211 beq L_Finished
212 mov R10, #0
213
214 Loop1:
215 add R2, R10, R10, LSR #1 @ Work out 3xcachelevel
216 mov R12, R6, LSR R2 @ bottom 3 bits are the Cache type for this level
217 and R12, R12, #7 @ get those 3 bits alone
218 cmp R12, #2
219 blt L_Skip @ no cache or only instruction cache at this level
220 mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
221 isb @ isb to sync the change to the CacheSizeID reg
222 mrc p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR)
223 and R2, R12, #0x7 @ extract the line length field
224 add R2, R2, #4 @ add 4 for the line length offset (log2 16 bytes)
225 @ ldr R4, =0x3FF
226 mov R4, #0x400
227 sub R4, R4, #1
228 ands R4, R4, R12, LSR #3 @ R4 is the max number on the way size (right aligned)
229 clz R5, R4 @ R5 is the bit position of the way size increment
230 @ ldr R7, =0x00007FFF
231 mov R7, #0x00008000
232 sub R7, R7, #1
233 ands R7, R7, R12, LSR #13 @ R7 is the max number of the index size (right aligned)
234
235 Loop2:
236 mov R9, R4 @ R9 working copy of the max way size (right aligned)
237
238 Loop3:
239 orr R0, R10, R9, LSL R5 @ factor in the way number and cache number into R11
240 orr R0, R0, R7, LSL R2 @ factor in the index number
241
242 blx R1
243
244 subs R9, R9, #1 @ decrement the way number
245 bge Loop3
246 subs R7, R7, #1 @ decrement the index
247 bge Loop2
248 L_Skip:
249 add R10, R10, #2 @ increment the cache number
250 cmp R3, R10
251 bgt Loop1
252
253 L_Finished:
254 dsb
255 ldmfd SP!, {r4-r12, lr}
256 bx LR
257
258 ASM_PFX(ArmDataMemoryBarrier):
259 dmb
260 bx LR
261
262 ASM_PFX(ArmDataSynchronizationBarrier):
263 dsb
264 bx LR
265
266 ASM_PFX(ArmInstructionSynchronizationBarrier):
267 isb
268 bx LR
269
270 ASM_PFX(ArmReadVBar):
271 # Set the Address of the Vector Table in the VBAR register
272 mrc p15, 0, r0, c12, c0, 0
273 bx lr
274
275 ASM_PFX(ArmWriteVBar):
276 # Set the Address of the Vector Table in the VBAR register
277 mcr p15, 0, r0, c12, c0, 0
278 # Ensure the SCTLR.V bit is clear
279 mrc p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
280 bic r0, r0, #0x00002000 @ clear V bit
281 mcr p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
282 isb
283 bx lr
284
285 ASM_PFX(ArmEnableVFP):
286 # Read CPACR (Coprocessor Access Control Register)
287 mrc p15, 0, r0, c1, c0, 2
288 # Enable VPF access (Full Access to CP10, CP11) (V* instructions)
289 orr r0, r0, #0x00f00000
290 # Write back CPACR (Coprocessor Access Control Register)
291 mcr p15, 0, r0, c1, c0, 2
292 isb
293 # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
294 mov r0, #0x40000000
295 mcr p10,#0x7,r0,c8,c0,#0
296 bx lr
297
298 ASM_PFX(ArmCallWFI):
299 wfi
300 bx lr
301
302 #Note: Return 0 in Uniprocessor implementation
303 ASM_PFX(ArmReadCbar):
304 mrc p15, 4, r0, c15, c0, 0 @ Read Configuration Base Address Register
305 bx lr
306
307 ASM_PFX(ArmReadMpidr):
308 mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
309 bx lr
310
311 ASM_PFX(ArmReadTpidrurw):
312 mrc p15, 0, r0, c13, c0, 2 @ read TPIDRURW
313 bx lr
314
315 ASM_PFX(ArmWriteTpidrurw):
316 mcr p15, 0, r0, c13, c0, 2 @ write TPIDRURW
317 bx lr
318
319 ASM_PFX(ArmIsArchTimerImplemented):
320 mrc p15, 0, r0, c0, c1, 1 @ Read ID_PFR1
321 and r0, r0, #0x000F0000
322 bx lr
323
324 ASM_PFX(ArmReadIdPfr1):
325 mrc p15, 0, r0, c0, c1, 1 @ Read ID_PFR1 Register
326 bx lr
327
328 ASM_PFX(ArmReadIdMmfr0):
329 mrc p15, 0, r0, c0, c1, 4 @ Read ID_MMFR0 Register
330 bx lr
331
332 ASM_FUNCTION_REMOVE_IF_UNREFERENCED