ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
   4 # Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
   5 #
   6 # This program and the accompanying materials
   7 # are licensed and made available under the terms and conditions of the BSD License
   8 # which accompanies this distribution.  The full text of the license may be found at
   9 # http://opensource.org/licenses/bsd-license.php
  10 #
  11 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 #
  14 #------------------------------------------------------------------------------
  15
  16 .text
  17 .align 2
  18
  19 GCC_ASM_EXPORT (ArmInvalidateInstructionCache)
  20 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)
  21 GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)
  22 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)
  23 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)
  24 GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)
  25 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay)
  26 GCC_ASM_EXPORT (ArmDrainWriteBuffer)
  27 GCC_ASM_EXPORT (ArmEnableMmu)
  28 GCC_ASM_EXPORT (ArmDisableMmu)
  29 GCC_ASM_EXPORT (ArmDisableCachesAndMmu)
  30 GCC_ASM_EXPORT (ArmMmuEnabled)
  31 GCC_ASM_EXPORT (ArmEnableDataCache)
  32 GCC_ASM_EXPORT (ArmDisableDataCache)
  33 GCC_ASM_EXPORT (ArmEnableInstructionCache)
  34 GCC_ASM_EXPORT (ArmDisableInstructionCache)
  35 GCC_ASM_EXPORT (ArmEnableSWPInstruction)
  36 GCC_ASM_EXPORT (ArmEnableBranchPrediction)
  37 GCC_ASM_EXPORT (ArmDisableBranchPrediction)
  38 GCC_ASM_EXPORT (ArmSetLowVectors)
  39 GCC_ASM_EXPORT (ArmSetHighVectors)
  40 GCC_ASM_EXPORT (ArmV7AllDataCachesOperation)
  41 GCC_ASM_EXPORT (ArmDataMemoryBarrier)
  42 GCC_ASM_EXPORT (ArmDataSynchronizationBarrier)
  43 GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)
  44 GCC_ASM_EXPORT (ArmReadVBar)
  45 GCC_ASM_EXPORT (ArmWriteVBar)
  46 GCC_ASM_EXPORT (ArmEnableVFP)
  47 GCC_ASM_EXPORT (ArmCallWFI)
  48 GCC_ASM_EXPORT (ArmReadCbar)
  49 GCC_ASM_EXPORT (ArmReadMpidr)
  50 GCC_ASM_EXPORT (ArmReadTpidrurw)
  51 GCC_ASM_EXPORT (ArmWriteTpidrurw)
  52 GCC_ASM_EXPORT (ArmIsArchTimerImplemented)
  53 GCC_ASM_EXPORT (ArmReadIdPfr1)
  54 GCC_ASM_EXPORT (ArmReadIdMmfr0)
  55
  56 .set DC_ON, (0x1<<2)
  57 .set IC_ON, (0x1<<12)
  58 .set CTRL_M_BIT,  (1 << 0)
  59 .set CTRL_C_BIT,  (1 << 2)
  60 .set CTRL_B_BIT,  (1 << 7)
  61 .set CTRL_I_BIT,  (1 << 12)
  62
  63
  64 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
  65   mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line
  66   bx      lr
  67
  68 ASM_PFX(ArmCleanDataCacheEntryByMVA):
  69   mcr     p15, 0, r0, c7, c10, 1  @clean single data cache line
  70   bx      lr
  71
  72
  73 ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
  74   mcr     p15, 0, r0, c7, c14, 1  @clean and invalidate single data cache line
  75   bx      lr
  76
  77
  78 ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
  79   mcr     p15, 0, r0, c7, c6, 2        @ Invalidate this line
  80   bx      lr
  81
  82
  83 ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
  84   mcr     p15, 0, r0, c7, c14, 2       @ Clean and Invalidate this line
  85   bx      lr
  86
  87
  88 ASM_PFX(ArmCleanDataCacheEntryBySetWay):
  89   mcr     p15, 0, r0, c7, c10, 2       @ Clean this line
  90   bx      lr
  91
  92 ASM_PFX(ArmInvalidateInstructionCache):
  93   mcr     p15,0,R0,c7,c5,0      @Invalidate entire instruction cache
  94   dsb
  95   isb
  96   bx      LR
  97
  98 ASM_PFX(ArmEnableMmu):
  99   mrc     p15,0,R0,c1,c0,0
 100   orr     R0,R0,#1
 101   mcr     p15,0,R0,c1,c0,0
 102   dsb
 103   isb
 104   bx      LR
 105
 106
 107 ASM_PFX(ArmDisableMmu):
 108   mrc     p15,0,R0,c1,c0,0
 109   bic     R0,R0,#1
 110   mcr     p15,0,R0,c1,c0,0      @Disable MMU
 111
 112   mcr     p15,0,R0,c8,c7,0      @Invalidate TLB
 113   mcr     p15,0,R0,c7,c5,6      @Invalidate Branch predictor array
 114   dsb
 115   isb
 116   bx      LR
 117
 118 ASM_PFX(ArmDisableCachesAndMmu):
 119   mrc   p15, 0, r0, c1, c0, 0           @ Get control register
 120   bic   r0, r0, #CTRL_M_BIT             @ Disable MMU
 121   bic   r0, r0, #CTRL_C_BIT             @ Disable D Cache
 122   bic   r0, r0, #CTRL_I_BIT             @ Disable I Cache
 123   mcr   p15, 0, r0, c1, c0, 0           @ Write control register
 124   dsb
 125   isb
 126   bx      LR
 127
 128 ASM_PFX(ArmMmuEnabled):
 129   mrc     p15,0,R0,c1,c0,0
 130   and     R0,R0,#1
 131   bx      LR
 132
 133 ASM_PFX(ArmEnableDataCache):
 134   ldr     R1,=DC_ON
 135   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 136   orr     R0,R0,R1              @Set C bit
 137   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 138   dsb
 139   isb
 140   bx      LR
 141
 142 ASM_PFX(ArmDisableDataCache):
 143   ldr     R1,=DC_ON
 144   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 145   bic     R0,R0,R1              @Clear C bit
 146   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 147   dsb
 148   isb
 149   bx      LR
 150
 151 ASM_PFX(ArmEnableInstructionCache):
 152   ldr     R1,=IC_ON
 153   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 154   orr     R0,R0,R1              @Set I bit
 155   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 156   dsb
 157   isb
 158   bx      LR
 159
 160 ASM_PFX(ArmDisableInstructionCache):
 161   ldr     R1,=IC_ON
 162   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 163   bic     R0,R0,R1              @Clear I bit.
 164   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 165   dsb
 166   isb
 167   bx      LR
 168
 169 ASM_PFX(ArmEnableSWPInstruction):
 170   mrc     p15, 0, r0, c1, c0, 0
 171   orr     r0, r0, #0x00000400
 172   mcr     p15, 0, r0, c1, c0, 0
 173   isb
 174   bx      LR
 175
 176 ASM_PFX(ArmEnableBranchPrediction):
 177   mrc     p15, 0, r0, c1, c0, 0
 178   orr     r0, r0, #0x00000800
 179   mcr     p15, 0, r0, c1, c0, 0
 180   dsb
 181   isb
 182   bx      LR
 183
 184 ASM_PFX(ArmDisableBranchPrediction):
 185   mrc     p15, 0, r0, c1, c0, 0
 186   bic     r0, r0, #0x00000800
 187   mcr     p15, 0, r0, c1, c0, 0
 188   dsb
 189   isb
 190   bx      LR
 191
 192 ASM_PFX(ArmSetLowVectors):
 193   mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
 194   bic     r0, r0, #0x00002000   @ clear V bit
 195   mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
 196   isb
 197   bx      LR
 198
 199 ASM_PFX(ArmSetHighVectors):
 200   mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
 201   orr     r0, r0, #0x00002000   @ Set V bit
 202   mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
 203   isb
 204   bx      LR
 205
 206 ASM_PFX(ArmV7AllDataCachesOperation):
 207   stmfd SP!,{r4-r12, LR}
 208   mov   R1, R0                @ Save Function call in R1
 209   mrc   p15, 1, R6, c0, c0, 1 @ Read CLIDR
 210   ands  R3, R6, #0x7000000    @ Mask out all but Level of Coherency (LoC)
 211   mov   R3, R3, LSR #23       @ Cache level value (naturally aligned)
 212   beq   L_Finished
 213   mov   R10, #0
 214
 215 Loop1:
 216   add   R2, R10, R10, LSR #1  @ Work out 3xcachelevel
 217   mov   R12, R6, LSR R2       @ bottom 3 bits are the Cache type for this level
 218   and   R12, R12, #7          @ get those 3 bits alone
 219   cmp   R12, #2
 220   blt   L_Skip                  @ no cache or only instruction cache at this level
 221   mcr   p15, 2, R10, c0, c0, 0  @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
 222   isb                           @ isb to sync the change to the CacheSizeID reg
 223   mrc   p15, 1, R12, c0, c0, 0  @ reads current Cache Size ID register (CCSIDR)
 224   and   R2, R12, #0x7           @ extract the line length field
 225   add   R2, R2, #4              @ add 4 for the line length offset (log2 16 bytes)
 226 @  ldr   R4, =0x3FF
 227   mov   R4, #0x400
 228   sub   R4, R4, #1
 229   ands  R4, R4, R12, LSR #3     @ R4 is the max number on the way size (right aligned)
 230   clz   R5, R4                  @ R5 is the bit position of the way size increment
 231 @  ldr   R7, =0x00007FFF
 232   mov   R7, #0x00008000
 233   sub   R7, R7, #1
 234   ands  R7, R7, R12, LSR #13    @ R7 is the max number of the index size (right aligned)
 235
 236 Loop2:
 237   mov   R9, R4                  @ R9 working copy of the max way size (right aligned)
 238
 239 Loop3:
 240   orr   R0, R10, R9, LSL R5     @ factor in the way number and cache number into R11
 241   orr   R0, R0, R7, LSL R2      @ factor in the index number
 242
 243   blx   R1
 244
 245   subs  R9, R9, #1              @ decrement the way number
 246   bge   Loop3
 247   subs  R7, R7, #1              @ decrement the index
 248   bge   Loop2
 249 L_Skip:
 250   add   R10, R10, #2            @ increment the cache number
 251   cmp   R3, R10
 252   bgt   Loop1
 253
 254 L_Finished:
 255   dsb
 256   ldmfd SP!, {r4-r12, lr}
 257   bx    LR
 258
 259 ASM_PFX(ArmDataMemoryBarrier):
 260   dmb
 261   bx      LR
 262
 263 ASM_PFX(ArmDataSynchronizationBarrier):
 264 ASM_PFX(ArmDrainWriteBuffer):
 265   dsb
 266   bx      LR
 267
 268 ASM_PFX(ArmInstructionSynchronizationBarrier):
 269   isb
 270   bx      LR
 271
 272 ASM_PFX(ArmReadVBar):
 273   # Set the Address of the Vector Table in the VBAR register
 274   mrc     p15, 0, r0, c12, c0, 0
 275   bx      lr
 276
 277 ASM_PFX(ArmWriteVBar):
 278   # Set the Address of the Vector Table in the VBAR register
 279   mcr     p15, 0, r0, c12, c0, 0
 280   # Ensure the SCTLR.V bit is clear
 281   mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
 282   bic     r0, r0, #0x00002000   @ clear V bit
 283   mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
 284   isb
 285   bx      lr
 286
 287 ASM_PFX(ArmEnableVFP):
 288   # Read CPACR (Coprocessor Access Control Register)
 289   mrc     p15, 0, r0, c1, c0, 2
 290   # Enable VPF access (Full Access to CP10, CP11) (V* instructions)
 291   orr     r0, r0, #0x00f00000
 292   # Write back CPACR (Coprocessor Access Control Register)
 293   mcr     p15, 0, r0, c1, c0, 2
 294   isb
 295   # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
 296   mov     r0, #0x40000000
 297   mcr     p10,#0x7,r0,c8,c0,#0
 298   bx      lr
 299
 300 ASM_PFX(ArmCallWFI):
 301   wfi
 302   bx      lr
 303
 304 #Note: Return 0 in Uniprocessor implementation
 305 ASM_PFX(ArmReadCbar):
 306   mrc     p15, 4, r0, c15, c0, 0  @ Read Configuration Base Address Register
 307   bx      lr
 308
 309 ASM_PFX(ArmReadMpidr):
 310   mrc     p15, 0, r0, c0, c0, 5       @ read MPIDR
 311   bx      lr
 312
 313 ASM_PFX(ArmReadTpidrurw):
 314   mrc     p15, 0, r0, c13, c0, 2    @ read TPIDRURW
 315   bx      lr
 316
 317 ASM_PFX(ArmWriteTpidrurw):
 318   mcr     p15, 0, r0, c13, c0, 2    @ write TPIDRURW
 319   bx      lr
 320
 321 ASM_PFX(ArmIsArchTimerImplemented):
 322   mrc    p15, 0, r0, c0, c1, 1     @ Read ID_PFR1
 323   and    r0, r0, #0x000F0000
 324   bx     lr
 325
 326 ASM_PFX(ArmReadIdPfr1):
 327   mrc    p15, 0, r0, c0, c1, 1     @ Read ID_PFR1 Register
 328   bx     lr
 329
 330 ASM_PFX(ArmReadIdMmfr0):
 331   mrc    p15, 0, r0, c0, c1, 4     @ Read ID_MMFR0 Register
 332   bx     lr
 333
 334 ASM_FUNCTION_REMOVE_IF_UNREFERENCED