ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008-2009 Apple Inc. All rights reserved.
   4 #
   5 # All rights reserved. This program and the accompanying materials
   6 # are licensed and made available under the terms and conditions of the BSD License
   7 # which accompanies this distribution.  The full text of the license may be found at
   8 # http://opensource.org/licenses/bsd-license.php
   9 #
  10 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 #
  13 #------------------------------------------------------------------------------
  14
  15 .globl ASM_PFX(ArmInvalidateInstructionCache)
  16 .globl ASM_PFX(ArmInvalidateDataCacheEntryByMVA)
  17 .globl ASM_PFX(ArmCleanDataCacheEntryByMVA)
  18 .globl ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA)
  19 .globl ASM_PFX(ArmInvalidateDataCacheEntryBySetWay)
  20 .globl ASM_PFX(ArmCleanDataCacheEntryBySetWay)
  21 .globl ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay)
  22 .globl ASM_PFX(ArmDrainWriteBuffer)
  23 .globl ASM_PFX(ArmEnableMmu)
  24 .globl ASM_PFX(ArmDisableMmu)
  25 .globl ASM_PFX(ArmMmuEnabled)
  26 .globl ASM_PFX(ArmEnableDataCache)
  27 .globl ASM_PFX(ArmDisableDataCache)
  28 .globl ASM_PFX(ArmEnableInstructionCache)
  29 .globl ASM_PFX(ArmDisableInstructionCache)
  30 .globl ASM_PFX(ArmEnableBranchPrediction)
  31 .globl ASM_PFX(ArmDisableBranchPrediction)
  32 .globl ASM_PFX(ArmV7AllDataCachesOperation)
  33 .globl ASM_PFX(ArmDataMemoryBarrier)
  34 .globl ASM_PFX(ArmDataSyncronizationBarrier)
  35 .globl ASM_PFX(ArmInstructionSynchronizationBarrier)
  36
  37 .text
  38 .align 2
  39
  40 .set DC_ON, (0x1<<2)
  41 .set IC_ON, (0x1<<12)
  42
  43
  44
  45 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
  46   mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line
  47   dsb
  48   isb
  49   bx      lr
  50
  51
  52 ASM_PFX(ArmCleanDataCacheEntryByMVA):
  53   mcr     p15, 0, r0, c7, c10, 1  @clean single data cache line
  54   dsb
  55   isb
  56   bx      lr
  57
  58
  59 ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
  60   mcr     p15, 0, r0, c7, c14, 1  @clean and invalidate single data cache line
  61   dsb
  62   isb
  63   bx      lr
  64
  65
  66 ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
  67   mcr     p15, 0, r0, c7, c6, 2        @ Invalidate this line
  68   dsb
  69   isb
  70   bx      lr
  71
  72
  73 ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
  74   mcr     p15, 0, r0, c7, c14, 2       @ Clean and Invalidate this line
  75   dsb
  76   isb
  77   bx      lr
  78
  79
  80 ASM_PFX(ArmCleanDataCacheEntryBySetWay):
  81   mcr     p15, 0, r0, c7, c10, 2       @ Clean this line
  82   dsb
  83   isb
  84   bx      lr
  85
  86
  87 ASM_PFX(ArmInvalidateInstructionCache):
  88   mcr     p15,0,R0,c7,c5,0      @Invalidate entire instruction cache
  89   dsb
  90   isb
  91   bx      LR
  92
  93 ASM_PFX(ArmEnableMmu):
  94   mrc     p15,0,R0,c1,c0,0
  95   orr     R0,R0,#1
  96   mcr     p15,0,R0,c1,c0,0
  97   dsb
  98   isb
  99   bx      LR
 100
 101 ASM_PFX(ArmMmuEnabled):
 102   mrc     p15,0,R0,c1,c0,0
 103   and     R0,R0,#1
 104   bx      LR
 105
 106 ASM_PFX(ArmDisableMmu):
 107   mrc     p15,0,R0,c1,c0,0
 108   bic     R0,R0,#1
 109   mcr     p15,0,R0,c1,c0,0      @Disable MMU
 110
 111         mcr             p15,0,R0,c8,c7,0      @Invalidate TLB
 112   mcr     p15,0,R0,c7,c5,6      @Invalidate Branch predictor array
 113   dsb
 114   isb
 115   bx      LR
 116
 117 ASM_PFX(ArmEnableDataCache):
 118   ldr     R1,=DC_ON
 119   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 120   orr     R0,R0,R1              @Set C bit
 121   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 122   dsb
 123   isb
 124   bx      LR
 125
 126 ASM_PFX(ArmDisableDataCache):
 127   ldr     R1,=DC_ON
 128   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 129   bic     R0,R0,R1              @Clear C bit
 130   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 131   dsb
 132   isb
 133   bx      LR
 134
 135 ASM_PFX(ArmEnableInstructionCache):
 136   ldr     R1,=IC_ON
 137   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 138   orr     R0,R0,R1              @Set I bit
 139   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 140   dsb
 141   isb
 142   bx      LR
 143
 144 ASM_PFX(ArmDisableInstructionCache):
 145   ldr     R1,=IC_ON
 146   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 147   bic     R0,R0,R1              @Clear I bit.
 148   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 149   dsb
 150   isb
 151   bx      LR
 152
 153 ASM_PFX(ArmEnableBranchPrediction):
 154   mrc     p15, 0, r0, c1, c0, 0
 155   orr     r0, r0, #0x00000800
 156   mcr     p15, 0, r0, c1, c0, 0
 157   dsb
 158   isb
 159   bx      LR
 160
 161 ASM_PFX(ArmDisableBranchPrediction):
 162   mrc     p15, 0, r0, c1, c0, 0
 163   bic     r0, r0, #0x00000800
 164   mcr     p15, 0, r0, c1, c0, 0
 165   dsb
 166   isb
 167   bx      LR
 168
 169
 170 ASM_PFX(ArmV7AllDataCachesOperation):
 171   stmfd SP!,{r4-r12, LR}
 172   mov   R1, R0                @ Save Function call in R1
 173   mrc   p15, 1, R6, c0, c0, 1 @ Read CLIDR
 174   ands  R3, R6, #0x7000000    @ Mask out all but Level of Coherency (LoC)
 175   mov   R3, R3, LSR #23       @ Cache level value (naturally aligned)
 176   beq   L_Finished
 177   mov   R10, #0
 178
 179 Loop1:
 180   add   R2, R10, R10, LSR #1  @ Work out 3xcachelevel
 181   mov   R12, R6, LSR R2       @ bottom 3 bits are the Cache type for this level
 182   and   R12, R12, #7          @ get those 3 bits alone
 183   cmp   R12, #2
 184   blt   L_Skip                  @ no cache or only instruction cache at this level
 185   mcr   p15, 2, R10, c0, c0, 0  @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
 186   isb                           @ isb to sync the change to the CacheSizeID reg
 187   mrc   p15, 1, R12, c0, c0, 0  @ reads current Cache Size ID register (CCSIDR)
 188   and   R2, R12, #0x7           @ extract the line length field
 189   add   R2, R2, #4              @ add 4 for the line length offset (log2 16 bytes)
 190 @  ldr   R4, =0x3FF
 191   mov   R4, #0x400
 192   sub   R4, R4, #1
 193   ands  R4, R4, R12, LSR #3     @ R4 is the max number on the way size (right aligned)
 194   clz   R5, R4                  @ R5 is the bit position of the way size increment
 195 @  ldr   R7, =0x00007FFF
 196   mov   R7, #0x00008000
 197   sub   R7, R7, #1
 198   ands  R7, R7, R12, LSR #13    @ R7 is the max number of the index size (right aligned)
 199
 200 Loop2:
 201   mov   R9, R4                  @ R9 working copy of the max way size (right aligned)
 202
 203 Loop3:
 204   orr   R0, R10, R9, LSL R5     @ factor in the way number and cache number into R11
 205   orr   R0, R0, R7, LSL R2      @ factor in the index number
 206
 207   blx   R1
 208
 209   subs  R9, R9, #1              @ decrement the way number
 210   bge   Loop3
 211   subs  R7, R7, #1              @ decrement the index
 212   bge   Loop2
 213 L_Skip:
 214   add   R10, R10, #2            @ increment the cache number
 215   cmp   R3, R10
 216   bgt   Loop1
 217
 218 L_Finished:
 219   dsb
 220   ldmfd SP!, {r4-r12, lr}
 221   bx    LR
 222
 223 ASM_PFX(ArmDataMemoryBarrier):
 224   dmb
 225   bx      LR
 226
 227 ASM_PFX(ArmDataSyncronizationBarrier):
 228 ASM_PFX(ArmDrainWriteBuffer):
 229   dsb
 230   bx      LR
 231
 232 ASM_PFX(ArmInstructionSynchronizationBarrier):
 233   isb
 234   bx      LR
 235
 236
 237 ASM_FUNCTION_REMOVE_IF_UNREFERENCED