1 #------------------------------------------------------------------------------
3 # Copyright (c) 2008-2009 Apple Inc. All rights reserved.
5 # All rights reserved. This program and the accompanying materials
6 # are licensed and made available under the terms and conditions of the BSD License
7 # which accompanies this distribution. The full text of the license may be found at
8 # http://opensource.org/licenses/bsd-license.php
10 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 #------------------------------------------------------------------------------
15 .globl ASM_PFX(ArmInvalidateInstructionCache)
16 .globl ASM_PFX(ArmInvalidateDataCacheEntryByMVA)
17 .globl ASM_PFX(ArmCleanDataCacheEntryByMVA)
18 .globl ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA)
19 .globl ASM_PFX(ArmInvalidateDataCacheEntryBySetWay)
20 .globl ASM_PFX(ArmCleanDataCacheEntryBySetWay)
21 .globl ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay)
22 .globl ASM_PFX(ArmDrainWriteBuffer)
23 .globl ASM_PFX(ArmEnableMmu)
24 .globl ASM_PFX(ArmDisableMmu)
25 .globl ASM_PFX(ArmMmuEnabled)
26 .globl ASM_PFX(ArmEnableDataCache)
27 .globl ASM_PFX(ArmDisableDataCache)
28 .globl ASM_PFX(ArmEnableInstructionCache)
29 .globl ASM_PFX(ArmDisableInstructionCache)
30 .globl ASM_PFX(ArmEnableBranchPrediction)
31 .globl ASM_PFX(ArmDisableBranchPrediction)
32 .globl ASM_PFX(ArmV7AllDataCachesOperation)
33 .globl ASM_PFX(ArmDataMemoryBarrier)
34 .globl ASM_PFX(ArmDataSyncronizationBarrier)
35 .globl ASM_PFX(ArmInstructionSynchronizationBarrier)
45 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
46 mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
52 ASM_PFX(ArmCleanDataCacheEntryByMVA):
53 mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
59 ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
60 mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line
66 ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
67 mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line
73 ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
74 mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line
80 ASM_PFX(ArmCleanDataCacheEntryBySetWay):
81 mcr p15, 0, r0, c7, c10, 2 @ Clean this line
87 ASM_PFX(ArmInvalidateInstructionCache):
88 mcr p15,0,R0,c7,c5,0 @Invalidate entire instruction cache
93 ASM_PFX(ArmEnableMmu):
101 ASM_PFX(ArmMmuEnabled):
106 ASM_PFX(ArmDisableMmu):
109 mcr p15,0,R0,c1,c0,0 @Disable MMU
111 mcr p15,0,R0,c8,c7,0 @Invalidate TLB
112 mcr p15,0,R0,c7,c5,6 @Invalidate Branch predictor array
117 ASM_PFX(ArmEnableDataCache):
119 mrc p15,0,R0,c1,c0,0 @Read control register configuration data
120 orr R0,R0,R1 @Set C bit
121 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
126 ASM_PFX(ArmDisableDataCache):
128 mrc p15,0,R0,c1,c0,0 @Read control register configuration data
129 bic R0,R0,R1 @Clear C bit
130 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
135 ASM_PFX(ArmEnableInstructionCache):
137 mrc p15,0,R0,c1,c0,0 @Read control register configuration data
138 orr R0,R0,R1 @Set I bit
139 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
144 ASM_PFX(ArmDisableInstructionCache):
146 mrc p15,0,R0,c1,c0,0 @Read control register configuration data
147 bic R0,R0,R1 @Clear I bit.
148 mcr p15,0,r0,c1,c0,0 @Write control register configuration data
153 ASM_PFX(ArmEnableBranchPrediction):
154 mrc p15, 0, r0, c1, c0, 0
155 orr r0, r0, #0x00000800
156 mcr p15, 0, r0, c1, c0, 0
161 ASM_PFX(ArmDisableBranchPrediction):
162 mrc p15, 0, r0, c1, c0, 0
163 bic r0, r0, #0x00000800
164 mcr p15, 0, r0, c1, c0, 0
170 ASM_PFX(ArmV7AllDataCachesOperation):
171 stmfd SP!,{r4-r12, LR}
172 mov R1, R0 @ Save Function call in R1
173 mrc p15, 1, R6, c0, c0, 1 @ Read CLIDR
174 ands R3, R6, #0x7000000 @ Mask out all but Level of Coherency (LoC)
175 mov R3, R3, LSR #23 @ Cache level value (naturally aligned)
180 add R2, R10, R10, LSR #1 @ Work out 3xcachelevel
181 mov R12, R6, LSR R2 @ bottom 3 bits are the Cache type for this level
182 and R12, R12, #7 @ get those 3 bits alone
184 blt L_Skip @ no cache or only instruction cache at this level
185 mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
186 isb @ isb to sync the change to the CacheSizeID reg
187 mrc p15, 1, R12, c0, c0, 0 @ reads current Cache Size ID register (CCSIDR)
188 and R2, R12, #0x7 @ extract the line length field
189 add R2, R2, #4 @ add 4 for the line length offset (log2 16 bytes)
193 ands R4, R4, R12, LSR #3 @ R4 is the max number on the way size (right aligned)
194 clz R5, R4 @ R5 is the bit position of the way size increment
195 @ ldr R7, =0x00007FFF
198 ands R7, R7, R12, LSR #13 @ R7 is the max number of the index size (right aligned)
201 mov R9, R4 @ R9 working copy of the max way size (right aligned)
204 orr R0, R10, R9, LSL R5 @ factor in the way number and cache number into R11
205 orr R0, R0, R7, LSL R2 @ factor in the index number
209 subs R9, R9, #1 @ decrement the way number
211 subs R7, R7, #1 @ decrement the index
214 add R10, R10, #2 @ increment the cache number
220 ldmfd SP!, {r4-r12, lr}
223 ASM_PFX(ArmDataMemoryBarrier):
227 ASM_PFX(ArmDataSyncronizationBarrier):
228 ASM_PFX(ArmDrainWriteBuffer):
232 ASM_PFX(ArmInstructionSynchronizationBarrier):
237 ASM_FUNCTION_REMOVE_IF_UNREFERENCED