ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4 #
   5 # This program and the accompanying materials
   6 # are licensed and made available under the terms and conditions of the BSD License
   7 # which accompanies this distribution.  The full text of the license may be found at
   8 # http://opensource.org/licenses/bsd-license.php
   9 #
  10 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 #
  13 #------------------------------------------------------------------------------
  14
  15 .text
  16 .align 2
  17
  18 GCC_ASM_EXPORT (ArmInvalidateInstructionCache)
  19 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)
  20 GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)
  21 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)
  22 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)
  23 GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)
  24 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay)
  25 GCC_ASM_EXPORT (ArmDrainWriteBuffer)
  26 GCC_ASM_EXPORT (ArmEnableMmu)
  27 GCC_ASM_EXPORT (ArmDisableMmu)
  28 GCC_ASM_EXPORT (ArmDisableCachesAndMmu)
  29 GCC_ASM_EXPORT (ArmMmuEnabled)
  30 GCC_ASM_EXPORT (ArmEnableDataCache)
  31 GCC_ASM_EXPORT (ArmDisableDataCache)
  32 GCC_ASM_EXPORT (ArmEnableInstructionCache)
  33 GCC_ASM_EXPORT (ArmDisableInstructionCache)
  34 GCC_ASM_EXPORT (ArmEnableSWPInstruction)
  35 GCC_ASM_EXPORT (ArmEnableBranchPrediction)
  36 GCC_ASM_EXPORT (ArmDisableBranchPrediction)
  37 GCC_ASM_EXPORT (ArmV7AllDataCachesOperation)
  38 GCC_ASM_EXPORT (ArmDataMemoryBarrier)
  39 GCC_ASM_EXPORT (ArmDataSyncronizationBarrier)
  40 GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)
  41 GCC_ASM_EXPORT (ArmWriteNsacr)
  42 GCC_ASM_EXPORT (ArmWriteScr)
  43 GCC_ASM_EXPORT (ArmWriteVMBar)
  44 GCC_ASM_EXPORT (ArmWriteVBar)
  45 GCC_ASM_EXPORT (ArmWriteCPACR)
  46 GCC_ASM_EXPORT (ArmEnableVFP)
  47 GCC_ASM_EXPORT (ArmCallWFI)
  48 GCC_ASM_EXPORT (ArmWriteAuxCr)
  49 GCC_ASM_EXPORT (ArmReadAuxCr)
  50 GCC_ASM_EXPORT (ArmReadCbar)
  51 GCC_ASM_EXPORT (ArmInvalidateInstructionAndDataTlb)
  52 GCC_ASM_EXPORT (ArmReadMpidr)
  53
  54 .set DC_ON, (0x1<<2)
  55 .set IC_ON, (0x1<<12)
  56 .set CTRL_M_BIT,  (1 << 0)
  57 .set CTRL_C_BIT,  (1 << 2)
  58 .set CTRL_B_BIT,  (1 << 7)
  59 .set CTRL_I_BIT,  (1 << 12)
  60
  61
  62 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
  63   mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line
  64   dsb
  65   isb
  66   bx      lr
  67
  68 ASM_PFX(ArmCleanDataCacheEntryByMVA):
  69   mcr     p15, 0, r0, c7, c10, 1  @clean single data cache line
  70   dsb
  71   isb
  72   bx      lr
  73
  74
  75 ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
  76   mcr     p15, 0, r0, c7, c14, 1  @clean and invalidate single data cache line
  77   dsb
  78   isb
  79   bx      lr
  80
  81
  82 ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
  83   mcr     p15, 0, r0, c7, c6, 2        @ Invalidate this line
  84   dsb
  85   isb
  86   bx      lr
  87
  88
  89 ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
  90   mcr     p15, 0, r0, c7, c14, 2       @ Clean and Invalidate this line
  91   dsb
  92   isb
  93   bx      lr
  94
  95
  96 ASM_PFX(ArmCleanDataCacheEntryBySetWay):
  97   mcr     p15, 0, r0, c7, c10, 2       @ Clean this line
  98   dsb
  99   isb
 100   bx      lr
 101
 102 ASM_PFX(ArmInvalidateInstructionCache):
 103   mcr     p15,0,R0,c7,c5,0      @Invalidate entire instruction cache
 104   dsb
 105   isb
 106   bx      LR
 107
 108 ASM_PFX(ArmEnableMmu):
 109   mrc     p15,0,R0,c1,c0,0
 110   orr     R0,R0,#1
 111   mcr     p15,0,R0,c1,c0,0
 112   dsb
 113   isb
 114   bx      LR
 115
 116
 117 ASM_PFX(ArmDisableMmu):
 118   mrc     p15,0,R0,c1,c0,0
 119   bic     R0,R0,#1
 120   mcr     p15,0,R0,c1,c0,0      @Disable MMU
 121
 122         mcr             p15,0,R0,c8,c7,0      @Invalidate TLB
 123   mcr     p15,0,R0,c7,c5,6      @Invalidate Branch predictor array
 124   dsb
 125   isb
 126   bx      LR
 127
 128 ASM_PFX(ArmDisableCachesAndMmu):
 129   mrc   p15, 0, r0, c1, c0, 0           @ Get control register
 130   bic   r0, r0, #CTRL_M_BIT             @ Disable MMU
 131   bic   r0, r0, #CTRL_C_BIT             @ Disable D Cache
 132   bic   r0, r0, #CTRL_I_BIT             @ Disable I Cache
 133   mcr   p15, 0, r0, c1, c0, 0           @ Write control register
 134   dsb
 135   isb
 136   bx      LR
 137
 138 ASM_PFX(ArmMmuEnabled):
 139   mrc     p15,0,R0,c1,c0,0
 140   and     R0,R0,#1
 141   bx      LR
 142
 143 ASM_PFX(ArmEnableDataCache):
 144   ldr     R1,=DC_ON
 145   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 146   orr     R0,R0,R1              @Set C bit
 147   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 148   dsb
 149   isb
 150   bx      LR
 151
 152 ASM_PFX(ArmDisableDataCache):
 153   ldr     R1,=DC_ON
 154   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 155   bic     R0,R0,R1              @Clear C bit
 156   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 157   dsb
 158   isb
 159   bx      LR
 160
 161 ASM_PFX(ArmEnableInstructionCache):
 162   ldr     R1,=IC_ON
 163   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 164   orr     R0,R0,R1              @Set I bit
 165   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 166   dsb
 167   isb
 168   bx      LR
 169
 170 ASM_PFX(ArmDisableInstructionCache):
 171   ldr     R1,=IC_ON
 172   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 173   bic     R0,R0,R1              @Clear I bit.
 174   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 175   dsb
 176   isb
 177   bx      LR
 178
 179 ASM_PFX(ArmEnableSWPInstruction):
 180   mrc     p15, 0, r0, c1, c0, 0
 181   orr     r0, r0, #0x00000400
 182   mcr     p15, 0, r0, c1, c0, 0
 183   isb
 184   bx      LR
 185
 186 ASM_PFX(ArmEnableBranchPrediction):
 187   mrc     p15, 0, r0, c1, c0, 0
 188   orr     r0, r0, #0x00000800
 189   mcr     p15, 0, r0, c1, c0, 0
 190   dsb
 191   isb
 192   bx      LR
 193
 194 ASM_PFX(ArmDisableBranchPrediction):
 195   mrc     p15, 0, r0, c1, c0, 0
 196   bic     r0, r0, #0x00000800
 197   mcr     p15, 0, r0, c1, c0, 0
 198   dsb
 199   isb
 200   bx      LR
 201
 202
 203 ASM_PFX(ArmV7AllDataCachesOperation):
 204   stmfd SP!,{r4-r12, LR}
 205   mov   R1, R0                @ Save Function call in R1
 206   mrc   p15, 1, R6, c0, c0, 1 @ Read CLIDR
 207   ands  R3, R6, #0x7000000    @ Mask out all but Level of Coherency (LoC)
 208   mov   R3, R3, LSR #23       @ Cache level value (naturally aligned)
 209   beq   L_Finished
 210   mov   R10, #0
 211
 212 Loop1:
 213   add   R2, R10, R10, LSR #1  @ Work out 3xcachelevel
 214   mov   R12, R6, LSR R2       @ bottom 3 bits are the Cache type for this level
 215   and   R12, R12, #7          @ get those 3 bits alone
 216   cmp   R12, #2
 217   blt   L_Skip                  @ no cache or only instruction cache at this level
 218   mcr   p15, 2, R10, c0, c0, 0  @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
 219   isb                           @ isb to sync the change to the CacheSizeID reg
 220   mrc   p15, 1, R12, c0, c0, 0  @ reads current Cache Size ID register (CCSIDR)
 221   and   R2, R12, #0x7           @ extract the line length field
 222   add   R2, R2, #4              @ add 4 for the line length offset (log2 16 bytes)
 223 @  ldr   R4, =0x3FF
 224   mov   R4, #0x400
 225   sub   R4, R4, #1
 226   ands  R4, R4, R12, LSR #3     @ R4 is the max number on the way size (right aligned)
 227   clz   R5, R4                  @ R5 is the bit position of the way size increment
 228 @  ldr   R7, =0x00007FFF
 229   mov   R7, #0x00008000
 230   sub   R7, R7, #1
 231   ands  R7, R7, R12, LSR #13    @ R7 is the max number of the index size (right aligned)
 232
 233 Loop2:
 234   mov   R9, R4                  @ R9 working copy of the max way size (right aligned)
 235
 236 Loop3:
 237   orr   R0, R10, R9, LSL R5     @ factor in the way number and cache number into R11
 238   orr   R0, R0, R7, LSL R2      @ factor in the index number
 239
 240   blx   R1
 241
 242   subs  R9, R9, #1              @ decrement the way number
 243   bge   Loop3
 244   subs  R7, R7, #1              @ decrement the index
 245   bge   Loop2
 246 L_Skip:
 247   add   R10, R10, #2            @ increment the cache number
 248   cmp   R3, R10
 249   bgt   Loop1
 250
 251 L_Finished:
 252   dsb
 253   ldmfd SP!, {r4-r12, lr}
 254   bx    LR
 255
 256 ASM_PFX(ArmDataMemoryBarrier):
 257   dmb
 258   bx      LR
 259
 260 ASM_PFX(ArmDataSyncronizationBarrier):
 261 ASM_PFX(ArmDrainWriteBuffer):
 262   dsb
 263   bx      LR
 264
 265 ASM_PFX(ArmInstructionSynchronizationBarrier):
 266   isb
 267   bx      LR
 268
 269 ASM_PFX(ArmWriteNsacr):
 270   mcr     p15, 0, r0, c1, c1, 2
 271   bx      lr
 272
 273 ASM_PFX(ArmWriteScr):
 274   mcr     p15, 0, r0, c1, c1, 0
 275   bx      lr
 276
 277 ASM_PFX(ArmWriteAuxCr):
 278   mcr     p15, 0, r0, c1, c0, 1
 279   bx      lr
 280
 281 ASM_PFX(ArmReadAuxCr):
 282   mrc     p15, 0, r0, c1, c0, 1
 283   bx      lr
 284
 285 ASM_PFX(ArmWriteVMBar):
 286   mcr     p15, 0, r0, c12, c0, 1
 287   bx      lr
 288
 289 ASM_PFX(ArmWriteVBar):
 290   mcr     p15, 0, r0, c12, c0, 0
 291   bx      lr
 292
 293 ASM_PFX(ArmWriteCPACR):
 294   mcr     p15, 0, r0, c1, c0, 2
 295   bx      lr
 296
 297 ASM_PFX(ArmEnableVFP):
 298   // Enable VFP registers
 299   mrc     p15, 0, r0, c1, c0, 2
 300   orr     r0, r0, #0x00f00000   // Enable VPF access (V* instructions)
 301   mcr     p15, 0, r0, c1, c0, 2
 302   mov     r0, #0x40000000       // Set EN bit in FPEXC
 303   mcr     p10,#0x7,r0,c8,c0,#0  // msr     FPEXC,r0 in ARM assembly
 304   bx      lr
 305
 306 ASM_PFX(ArmCallWFI):
 307   wfi
 308   bx      lr
 309
 310 //Note: Return 0 in Uniprocessor implementation
 311 ASM_PFX(ArmReadCbar):
 312   mrc     p15, 4, r0, c15, c0, 0        //Read Configuration Base Address Register
 313   bx      lr
 314
 315 ASM_PFX(ArmInvalidateInstructionAndDataTlb):
 316   mcr     p15, 0, r0, c8, c7, 0      @ Invalidate Inst TLB and Data TLB
 317   dsb
 318   bx lr
 319
 320 ASM_PFX(ArmReadMpidr):
 321   mrc     p15, 0, r0, c0, c0, 5      @ read MPIDR
 322   bx      lr
 323
 324 ASM_FUNCTION_REMOVE_IF_UNREFERENCED