ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
   4 # Copyright (c) 2011, ARM Limited. All rights reserved.
   5 #
   6 # This program and the accompanying materials
   7 # are licensed and made available under the terms and conditions of the BSD License
   8 # which accompanies this distribution.  The full text of the license may be found at
   9 # http://opensource.org/licenses/bsd-license.php
  10 #
  11 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 #
  14 #------------------------------------------------------------------------------
  15
  16 .text
  17 .align 2
  18
  19 GCC_ASM_EXPORT (ArmInvalidateInstructionCache)
  20 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryByMVA)
  21 GCC_ASM_EXPORT (ArmCleanDataCacheEntryByMVA)
  22 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryByMVA)
  23 GCC_ASM_EXPORT (ArmInvalidateDataCacheEntryBySetWay)
  24 GCC_ASM_EXPORT (ArmCleanDataCacheEntryBySetWay)
  25 GCC_ASM_EXPORT (ArmCleanInvalidateDataCacheEntryBySetWay)
  26 GCC_ASM_EXPORT (ArmDrainWriteBuffer)
  27 GCC_ASM_EXPORT (ArmEnableMmu)
  28 GCC_ASM_EXPORT (ArmDisableMmu)
  29 GCC_ASM_EXPORT (ArmDisableCachesAndMmu)
  30 GCC_ASM_EXPORT (ArmMmuEnabled)
  31 GCC_ASM_EXPORT (ArmEnableDataCache)
  32 GCC_ASM_EXPORT (ArmDisableDataCache)
  33 GCC_ASM_EXPORT (ArmEnableInstructionCache)
  34 GCC_ASM_EXPORT (ArmDisableInstructionCache)
  35 GCC_ASM_EXPORT (ArmEnableSWPInstruction)
  36 GCC_ASM_EXPORT (ArmEnableBranchPrediction)
  37 GCC_ASM_EXPORT (ArmDisableBranchPrediction)
  38 GCC_ASM_EXPORT (ArmSetLowVectors)
  39 GCC_ASM_EXPORT (ArmSetHighVectors)
  40 GCC_ASM_EXPORT (ArmV7AllDataCachesOperation)
  41 GCC_ASM_EXPORT (ArmDataMemoryBarrier)
  42 GCC_ASM_EXPORT (ArmDataSyncronizationBarrier)
  43 GCC_ASM_EXPORT (ArmInstructionSynchronizationBarrier)
  44 GCC_ASM_EXPORT (ArmWriteVBar)
  45 GCC_ASM_EXPORT (ArmEnableVFP)
  46 GCC_ASM_EXPORT (ArmCallWFI)
  47 GCC_ASM_EXPORT (ArmReadCbar)
  48 GCC_ASM_EXPORT (ArmInvalidateInstructionAndDataTlb)
  49 GCC_ASM_EXPORT (ArmReadMpidr)
  50 GCC_ASM_EXPORT (ArmReadTpidrurw)
  51 GCC_ASM_EXPORT (ArmWriteTpidrurw)
  52 GCC_ASM_EXPORT (ArmIsArchTimerImplemented)
  53 GCC_ASM_EXPORT (ArmReadIdPfr1)
  54
  55 .set DC_ON, (0x1<<2)
  56 .set IC_ON, (0x1<<12)
  57 .set CTRL_M_BIT,  (1 << 0)
  58 .set CTRL_C_BIT,  (1 << 2)
  59 .set CTRL_B_BIT,  (1 << 7)
  60 .set CTRL_I_BIT,  (1 << 12)
  61
  62
  63 ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
  64   mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line
  65   dsb
  66   isb
  67   bx      lr
  68
  69 ASM_PFX(ArmCleanDataCacheEntryByMVA):
  70   mcr     p15, 0, r0, c7, c10, 1  @clean single data cache line
  71   dsb
  72   isb
  73   bx      lr
  74
  75
  76 ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
  77   mcr     p15, 0, r0, c7, c14, 1  @clean and invalidate single data cache line
  78   dsb
  79   isb
  80   bx      lr
  81
  82
  83 ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
  84   mcr     p15, 0, r0, c7, c6, 2        @ Invalidate this line
  85   dsb
  86   isb
  87   bx      lr
  88
  89
  90 ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
  91   mcr     p15, 0, r0, c7, c14, 2       @ Clean and Invalidate this line
  92   dsb
  93   isb
  94   bx      lr
  95
  96
  97 ASM_PFX(ArmCleanDataCacheEntryBySetWay):
  98   mcr     p15, 0, r0, c7, c10, 2       @ Clean this line
  99   dsb
 100   isb
 101   bx      lr
 102
 103 ASM_PFX(ArmInvalidateInstructionCache):
 104   mcr     p15,0,R0,c7,c5,0      @Invalidate entire instruction cache
 105   dsb
 106   isb
 107   bx      LR
 108
 109 ASM_PFX(ArmEnableMmu):
 110   mrc     p15,0,R0,c1,c0,0
 111   orr     R0,R0,#1
 112   mcr     p15,0,R0,c1,c0,0
 113   dsb
 114   isb
 115   bx      LR
 116
 117
 118 ASM_PFX(ArmDisableMmu):
 119   mrc     p15,0,R0,c1,c0,0
 120   bic     R0,R0,#1
 121   mcr     p15,0,R0,c1,c0,0      @Disable MMU
 122
 123   mcr     p15,0,R0,c8,c7,0      @Invalidate TLB
 124   mcr     p15,0,R0,c7,c5,6      @Invalidate Branch predictor array
 125   dsb
 126   isb
 127   bx      LR
 128
 129 ASM_PFX(ArmDisableCachesAndMmu):
 130   mrc   p15, 0, r0, c1, c0, 0           @ Get control register
 131   bic   r0, r0, #CTRL_M_BIT             @ Disable MMU
 132   bic   r0, r0, #CTRL_C_BIT             @ Disable D Cache
 133   bic   r0, r0, #CTRL_I_BIT             @ Disable I Cache
 134   mcr   p15, 0, r0, c1, c0, 0           @ Write control register
 135   dsb
 136   isb
 137   bx      LR
 138
 139 ASM_PFX(ArmMmuEnabled):
 140   mrc     p15,0,R0,c1,c0,0
 141   and     R0,R0,#1
 142   bx      LR
 143
 144 ASM_PFX(ArmEnableDataCache):
 145   ldr     R1,=DC_ON
 146   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 147   orr     R0,R0,R1              @Set C bit
 148   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 149   dsb
 150   isb
 151   bx      LR
 152
 153 ASM_PFX(ArmDisableDataCache):
 154   ldr     R1,=DC_ON
 155   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 156   bic     R0,R0,R1              @Clear C bit
 157   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 158   dsb
 159   isb
 160   bx      LR
 161
 162 ASM_PFX(ArmEnableInstructionCache):
 163   ldr     R1,=IC_ON
 164   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 165   orr     R0,R0,R1              @Set I bit
 166   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 167   dsb
 168   isb
 169   bx      LR
 170
 171 ASM_PFX(ArmDisableInstructionCache):
 172   ldr     R1,=IC_ON
 173   mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
 174   bic     R0,R0,R1              @Clear I bit.
 175   mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
 176   dsb
 177   isb
 178   bx      LR
 179
 180 ASM_PFX(ArmEnableSWPInstruction):
 181   mrc     p15, 0, r0, c1, c0, 0
 182   orr     r0, r0, #0x00000400
 183   mcr     p15, 0, r0, c1, c0, 0
 184   isb
 185   bx      LR
 186
 187 ASM_PFX(ArmEnableBranchPrediction):
 188   mrc     p15, 0, r0, c1, c0, 0
 189   orr     r0, r0, #0x00000800
 190   mcr     p15, 0, r0, c1, c0, 0
 191   dsb
 192   isb
 193   bx      LR
 194
 195 ASM_PFX(ArmDisableBranchPrediction):
 196   mrc     p15, 0, r0, c1, c0, 0
 197   bic     r0, r0, #0x00000800
 198   mcr     p15, 0, r0, c1, c0, 0
 199   dsb
 200   isb
 201   bx      LR
 202
 203 ASM_PFX(ArmSetLowVectors):
 204   mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
 205   bic     r0, r0, #0x00002000   @ clear V bit
 206   mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
 207   isb
 208   bx      LR
 209
 210 ASM_PFX(ArmSetHighVectors):
 211   mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
 212   orr     r0, r0, #0x00002000   @ clear V bit
 213   mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
 214   isb
 215   bx      LR
 216
 217 ASM_PFX(ArmV7AllDataCachesOperation):
 218   stmfd SP!,{r4-r12, LR}
 219   mov   R1, R0                @ Save Function call in R1
 220   mrc   p15, 1, R6, c0, c0, 1 @ Read CLIDR
 221   ands  R3, R6, #0x7000000    @ Mask out all but Level of Coherency (LoC)
 222   mov   R3, R3, LSR #23       @ Cache level value (naturally aligned)
 223   beq   L_Finished
 224   mov   R10, #0
 225
 226 Loop1:
 227   add   R2, R10, R10, LSR #1  @ Work out 3xcachelevel
 228   mov   R12, R6, LSR R2       @ bottom 3 bits are the Cache type for this level
 229   and   R12, R12, #7          @ get those 3 bits alone
 230   cmp   R12, #2
 231   blt   L_Skip                  @ no cache or only instruction cache at this level
 232   mcr   p15, 2, R10, c0, c0, 0  @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
 233   isb                           @ isb to sync the change to the CacheSizeID reg
 234   mrc   p15, 1, R12, c0, c0, 0  @ reads current Cache Size ID register (CCSIDR)
 235   and   R2, R12, #0x7           @ extract the line length field
 236   add   R2, R2, #4              @ add 4 for the line length offset (log2 16 bytes)
 237 @  ldr   R4, =0x3FF
 238   mov   R4, #0x400
 239   sub   R4, R4, #1
 240   ands  R4, R4, R12, LSR #3     @ R4 is the max number on the way size (right aligned)
 241   clz   R5, R4                  @ R5 is the bit position of the way size increment
 242 @  ldr   R7, =0x00007FFF
 243   mov   R7, #0x00008000
 244   sub   R7, R7, #1
 245   ands  R7, R7, R12, LSR #13    @ R7 is the max number of the index size (right aligned)
 246
 247 Loop2:
 248   mov   R9, R4                  @ R9 working copy of the max way size (right aligned)
 249
 250 Loop3:
 251   orr   R0, R10, R9, LSL R5     @ factor in the way number and cache number into R11
 252   orr   R0, R0, R7, LSL R2      @ factor in the index number
 253
 254   blx   R1
 255
 256   subs  R9, R9, #1              @ decrement the way number
 257   bge   Loop3
 258   subs  R7, R7, #1              @ decrement the index
 259   bge   Loop2
 260 L_Skip:
 261   add   R10, R10, #2            @ increment the cache number
 262   cmp   R3, R10
 263   bgt   Loop1
 264
 265 L_Finished:
 266   dsb
 267   ldmfd SP!, {r4-r12, lr}
 268   bx    LR
 269
 270 ASM_PFX(ArmDataMemoryBarrier):
 271   dmb
 272   bx      LR
 273
 274 ASM_PFX(ArmDataSyncronizationBarrier):
 275 ASM_PFX(ArmDrainWriteBuffer):
 276   dsb
 277   bx      LR
 278
 279 ASM_PFX(ArmInstructionSynchronizationBarrier):
 280   isb
 281   bx      LR
 282
 283 ASM_PFX(ArmWriteVBar):
 284   # Set the Address of the Vector Table in the VBAR register
 285   mcr     p15, 0, r0, c12, c0, 0
 286   # Ensure the SCTLR.V bit is clear
 287   mrc     p15, 0, r0, c1, c0, 0 @ Read SCTLR into R0 (Read control register configuration data)
 288   bic     r0, r0, #0x00002000   @ clear V bit
 289   mcr     p15, 0, r0, c1, c0, 0 @ Write R0 into SCTLR (Write control register configuration data)
 290   isb
 291   bx      lr
 292
 293 ASM_PFX(ArmEnableVFP):
 294   # Read CPACR (Coprocessor Access Control Register)
 295   mrc     p15, 0, r0, c1, c0, 2
 296   # Enable VPF access (Full Access to CP10, CP11) (V* instructions)
 297   orr     r0, r0, #0x00f00000
 298   # Write back CPACR (Coprocessor Access Control Register)
 299   mcr     p15, 0, r0, c1, c0, 2
 300   # Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
 301   mov     r0, #0x40000000
 302   mcr     p10,#0x7,r0,c8,c0,#0
 303   bx      lr
 304
 305 ASM_PFX(ArmCallWFI):
 306   wfi
 307   bx      lr
 308
 309 #Note: Return 0 in Uniprocessor implementation
 310 ASM_PFX(ArmReadCbar):
 311   mrc     p15, 4, r0, c15, c0, 0  @ Read Configuration Base Address Register
 312   bx      lr
 313
 314 ASM_PFX(ArmInvalidateInstructionAndDataTlb):
 315   mcr     p15, 0, r0, c8, c7, 0      @ Invalidate Inst TLB and Data TLB
 316   dsb
 317   bx lr
 318
 319 ASM_PFX(ArmReadMpidr):
 320   mrc     p15, 0, r0, c0, c0, 5       @ read MPIDR
 321   bx      lr
 322
 323 ASM_PFX(ArmReadTpidrurw):
 324   mrc     p15, 0, r0, c13, c0, 2    @ read TPIDRURW
 325   bx      lr
 326
 327 ASM_PFX(ArmWriteTpidrurw):
 328   mcr     p15, 0, r0, c13, c0, 2    @ write TPIDRURW
 329   bx      lr
 330
 331 ASM_PFX(ArmIsArchTimerImplemented):
 332   mrc    p15, 0, r0, c0, c1, 1     @ Read ID_PFR1
 333   and    r0, r0, #0x000F0000
 334   bx     lr
 335
 336 ASM_PFX(ArmReadIdPfr1):
 337   mrc    p15, 0, r0, c0, c1, 1     @ Read ID_PFR1 Register
 338   bx     lr
 339
 340 ASM_FUNCTION_REMOVE_IF_UNREFERENCED