1 //------------------------------------------------------------------------------
3 // Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
4 // Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
6 // This program and the accompanying materials
7 // are licensed and made available under the terms and conditions of the BSD License
8 // which accompanies this distribution. The full text of the license may be found at
9 // http://opensource.org/licenses/bsd-license.php
11 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14 //------------------------------------------------------------------------------
16 EXPORT ArmInvalidateInstructionCache
17 EXPORT ArmInvalidateDataCacheEntryByMVA
18 EXPORT ArmCleanDataCacheEntryByMVA
19 EXPORT ArmCleanInvalidateDataCacheEntryByMVA
20 EXPORT ArmInvalidateDataCacheEntryBySetWay
21 EXPORT ArmCleanDataCacheEntryBySetWay
22 EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
23 EXPORT ArmDrainWriteBuffer
26 EXPORT ArmDisableCachesAndMmu
28 EXPORT ArmEnableDataCache
29 EXPORT ArmDisableDataCache
30 EXPORT ArmEnableInstructionCache
31 EXPORT ArmDisableInstructionCache
32 EXPORT ArmEnableSWPInstruction
33 EXPORT ArmEnableBranchPrediction
34 EXPORT ArmDisableBranchPrediction
35 EXPORT ArmSetLowVectors
36 EXPORT ArmSetHighVectors
37 EXPORT ArmV7AllDataCachesOperation
38 EXPORT ArmV7PerformPoUDataCacheOperation
39 EXPORT ArmDataMemoryBarrier
40 EXPORT ArmDataSyncronizationBarrier
41 EXPORT ArmInstructionSynchronizationBarrier
48 EXPORT ArmReadTpidrurw
49 EXPORT ArmWriteTpidrurw
50 EXPORT ArmIsArchTimerImplemented
53 AREA ArmV7Support, CODE, READONLY
56 DC_ON EQU ( 0x1:SHL:2 )
57 IC_ON EQU ( 0x1:SHL:12 )
58 CTRL_M_BIT EQU (1 << 0)
59 CTRL_C_BIT EQU (1 << 2)
60 CTRL_B_BIT EQU (1 << 7)
61 CTRL_I_BIT EQU (1 << 12)
64 ArmInvalidateDataCacheEntryByMVA
65 mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
70 ArmCleanDataCacheEntryByMVA
71 mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
77 ArmCleanInvalidateDataCacheEntryByMVA
78 mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
84 ArmInvalidateDataCacheEntryBySetWay
85 mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
91 ArmCleanInvalidateDataCacheEntryBySetWay
92 mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
98 ArmCleanDataCacheEntryBySetWay
99 mcr p15, 0, r0, c7, c10, 2 ; Clean this line
105 ArmInvalidateInstructionCache
106 mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
111 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
112 orr R0,R0,#1 ; Set SCTLR.M bit : Enable MMU
113 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
119 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
120 bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU
121 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
123 mcr p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB
124 mcr p15,0,R0,c7,c5,6 ; BPIALL : Invalidate entire branch predictor array
129 ArmDisableCachesAndMmu
130 mrc p15, 0, r0, c1, c0, 0 ; Get control register
131 bic r0, r0, #CTRL_M_BIT ; Disable MMU
132 bic r0, r0, #CTRL_C_BIT ; Disable D Cache
133 bic r0, r0, #CTRL_I_BIT ; Disable I Cache
134 mcr p15, 0, r0, c1, c0, 0 ; Write control register
140 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
145 ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
146 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
147 orr R0,R0,R1 ; Set SCTLR.C bit : Data and unified caches enabled
148 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
154 ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
155 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
156 bic R0,R0,R1 ; Clear SCTLR.C bit : Data and unified caches disabled
157 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
162 ArmEnableInstructionCache
163 ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit
164 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
165 orr R0,R0,R1 ; Set SCTLR.I bit : Instruction caches enabled
166 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
171 ArmDisableInstructionCache
172 ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit
173 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
174 BIC R0,R0,R1 ; Clear SCTLR.I bit : Instruction caches disabled
175 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
179 ArmEnableSWPInstruction
180 mrc p15, 0, r0, c1, c0, 0
181 orr r0, r0, #0x00000400
182 mcr p15, 0, r0, c1, c0, 0
186 ArmEnableBranchPrediction
187 mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
188 orr r0, r0, #0x00000800 ;
189 mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
194 ArmDisableBranchPrediction
195 mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
196 bic r0, r0, #0x00000800 ;
197 mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
203 mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
204 bic r0, r0, #0x00002000 ; clear V bit
205 mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
210 mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
211 orr r0, r0, #0x00002000 ; Set V bit
212 mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
216 ArmV7AllDataCachesOperation
217 stmfd SP!,{r4-r12, LR}
218 mov R1, R0 ; Save Function call in R1
219 mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR
220 ands R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC)
221 mov R3, R3, LSR #23 ; Cache level value (naturally aligned)
226 add R2, R10, R10, LSR #1 ; Work out 3xcachelevel
227 mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level
228 and R12, R12, #7 ; get those 3 bits alone
230 blt Skip ; no cache or only instruction cache at this level
231 mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
232 isb ; isb to sync the change to the CacheSizeID reg
233 mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)
234 and R2, R12, #&7 ; extract the line length field
235 add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)
237 ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)
238 clz R5, R4 ; R5 is the bit position of the way size increment
240 ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)
243 mov R9, R4 ; R9 working copy of the max way size (right aligned)
246 orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11
247 orr R0, R0, R7, LSL R2 ; factor in the index number
251 subs R9, R9, #1 ; decrement the way number
253 subs R7, R7, #1 ; decrement the index
256 add R10, R10, #2 ; increment the cache number
262 ldmfd SP!, {r4-r12, lr}
265 ArmV7PerformPoUDataCacheOperation
266 stmfd SP!,{r4-r12, LR}
267 mov R1, R0 ; Save Function call in R1
268 mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR
269 ands R3, R6, #&38000000 ; Mask out all but Level of Unification (LoU)
270 mov R3, R3, LSR #26 ; Cache level value (naturally aligned)
275 add R2, R10, R10, LSR #1 ; Work out 3xcachelevel
276 mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level
277 and R12, R12, #7 ; get those 3 bits alone
279 blt Skip2 ; no cache or only instruction cache at this level
280 mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
281 isb ; isb to sync the change to the CacheSizeID reg
282 mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)
283 and R2, R12, #&7 ; extract the line length field
284 add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)
286 ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)
287 clz R5, R4 ; R5 is the bit position of the way size increment
289 ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)
292 mov R9, R4 ; R9 working copy of the max way size (right aligned)
295 orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11
296 orr R0, R0, R7, LSL R2 ; factor in the index number
300 subs R9, R9, #1 ; decrement the way number
302 subs R7, R7, #1 ; decrement the index
305 add R10, R10, #2 ; increment the cache number
311 ldmfd SP!, {r4-r12, lr}
318 ArmDataSyncronizationBarrier
323 ArmInstructionSynchronizationBarrier
328 // Set the Address of the Vector Table in the VBAR register
329 mrc p15, 0, r0, c12, c0, 0
333 // Set the Address of the Vector Table in the VBAR register
334 mcr p15, 0, r0, c12, c0, 0
335 // Ensure the SCTLR.V bit is clear
336 mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
337 bic r0, r0, #0x00002000 ; clear V bit
338 mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
343 // Read CPACR (Coprocessor Access Control Register)
344 mrc p15, 0, r0, c1, c0, 2
345 // Enable VPF access (Full Access to CP10, CP11) (V* instructions)
346 orr r0, r0, #0x00f00000
347 // Write back CPACR (Coprocessor Access Control Register)
348 mcr p15, 0, r0, c1, c0, 2
350 // Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
352 mcr p10,#0x7,r0,c8,c0,#0
359 //Note: Return 0 in Uniprocessor implementation
361 mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register
365 mrc p15, 0, r0, c0, c0, 5 ; read MPIDR
369 mrc p15, 0, r0, c13, c0, 2 ; read TPIDRURW
373 mcr p15, 0, r0, c13, c0, 2 ; write TPIDRURW
376 ArmIsArchTimerImplemented
377 mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1
378 and r0, r0, #0x000F0000
382 mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1 Register