ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm

   1 //------------------------------------------------------------------------------
   2 //
   3 // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4 //
   5 // This program and the accompanying materials
   6 // are licensed and made available under the terms and conditions of the BSD License
   7 // which accompanies this distribution.  The full text of the license may be found at
   8 // http://opensource.org/licenses/bsd-license.php
   9 //
  10 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 //
  13 //------------------------------------------------------------------------------
  14
  15     EXPORT  ArmInvalidateInstructionCache
  16     EXPORT  ArmInvalidateDataCacheEntryByMVA
  17     EXPORT  ArmCleanDataCacheEntryByMVA
  18     EXPORT  ArmCleanInvalidateDataCacheEntryByMVA
  19     EXPORT  ArmInvalidateDataCacheEntryBySetWay
  20     EXPORT  ArmCleanDataCacheEntryBySetWay
  21     EXPORT  ArmCleanInvalidateDataCacheEntryBySetWay
  22     EXPORT  ArmDrainWriteBuffer
  23     EXPORT  ArmEnableMmu
  24     EXPORT  ArmDisableMmu
  25     EXPORT  ArmDisableCachesAndMmu
  26     EXPORT  ArmMmuEnabled
  27     EXPORT  ArmEnableDataCache
  28     EXPORT  ArmDisableDataCache
  29     EXPORT  ArmEnableInstructionCache
  30     EXPORT  ArmDisableInstructionCache
  31     EXPORT  ArmEnableSWPInstruction
  32     EXPORT  ArmEnableBranchPrediction
  33     EXPORT  ArmDisableBranchPrediction
  34     EXPORT  ArmV7AllDataCachesOperation
  35     EXPORT  ArmDataMemoryBarrier
  36     EXPORT  ArmDataSyncronizationBarrier
  37     EXPORT  ArmInstructionSynchronizationBarrier
  38     EXPORT  ArmWriteNsacr
  39     EXPORT  ArmWriteScr
  40     EXPORT  ArmWriteVMBar
  41     EXPORT  ArmWriteVBar
  42     EXPORT  ArmReadVBar
  43     EXPORT  ArmWriteCPACR
  44     EXPORT  ArmEnableVFP
  45     EXPORT  ArmCallWFI
  46     EXPORT  ArmWriteAuxCr
  47     EXPORT  ArmReadAuxCr
  48     EXPORT  ArmReadCbar
  49     EXPORT  ArmInvalidateInstructionAndDataTlb
  50     EXPORT  ArmReadMpidr
  51
  52     AREA    ArmCacheLib, CODE, READONLY
  53     PRESERVE8
  54
  55 DC_ON           EQU     ( 0x1:SHL:2 )
  56 IC_ON           EQU     ( 0x1:SHL:12 )
  57 CTRL_M_BIT      EQU     (1 << 0)
  58 CTRL_C_BIT      EQU     (1 << 2)
  59 CTRL_B_BIT      EQU     (1 << 7)
  60 CTRL_I_BIT      EQU     (1 << 12)
  61
  62
  63 ArmInvalidateDataCacheEntryByMVA
  64   mcr     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line
  65   dsb
  66   isb
  67   bx      lr
  68
  69
  70 ArmCleanDataCacheEntryByMVA
  71   mcr     p15, 0, r0, c7, c10, 1  ; clean single data cache line
  72   dsb
  73   isb
  74   bx      lr
  75
  76
  77 ArmCleanInvalidateDataCacheEntryByMVA
  78   mcr     p15, 0, r0, c7, c14, 1  ; clean and invalidate single data cache line
  79   dsb
  80   isb
  81   bx      lr
  82
  83
  84 ArmInvalidateDataCacheEntryBySetWay
  85   mcr     p15, 0, r0, c7, c6, 2        ; Invalidate this line\s\s\s\s
  86   dsb
  87   isb
  88   bx      lr
  89
  90
  91 ArmCleanInvalidateDataCacheEntryBySetWay
  92   mcr     p15, 0, r0, c7, c14, 2       ; Clean and Invalidate this line\s\s\s\s
  93   dsb
  94   isb
  95   bx      lr
  96
  97
  98 ArmCleanDataCacheEntryBySetWay
  99   mcr     p15, 0, r0, c7, c10, 2       ; Clean this line\s\s\s\s
 100   dsb
 101   isb
 102   bx      lr
 103
 104
 105 ArmInvalidateInstructionCache
 106   mcr     p15,0,R0,c7,c5,0      ;Invalidate entire instruction cache
 107   isb
 108   bx      LR
 109
 110 ArmEnableMmu
 111   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 112   orr     R0,R0,#1              ; Set SCTLR.M bit : Enable MMU
 113   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 114   dsb
 115   isb
 116   bx      LR
 117
 118 ArmMmuEnabled
 119   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 120   and     R0,R0,#1
 121   bx      LR
 122
 123 ArmDisableMmu
 124   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 125   bic     R0,R0,#1              ; Clear SCTLR.M bit : Disable MMU
 126   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 127
 128   mcr \s\s  p15,0,R0,c8,c7,0      ; TLBIALL : Invalidate unified TLB
 129   mcr     p15,0,R0,c7,c5,6      ; BPIALL  : Invalidate entire branch predictor array
 130   dsb
 131   isb
 132   bx      LR
 133
 134 ArmDisableCachesAndMmu
 135   mrc   p15, 0, r0, c1, c0, 0           ; Get control register
 136   bic   r0, r0, #CTRL_M_BIT             ; Disable MMU
 137   bic   r0, r0, #CTRL_C_BIT             ; Disable D Cache
 138   bic   r0, r0, #CTRL_I_BIT             ; Disable I Cache
 139   mcr   p15, 0, r0, c1, c0, 0           ; Write control register
 140   dsb
 141   isb
 142   bx      LR
 143
 144 ArmEnableDataCache
 145   ldr     R1,=DC_ON             ; Specify SCTLR.C bit : (Data) Cache enable bit
 146   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 147   orr     R0,R0,R1              ; Set SCTLR.C bit : Data and unified caches enabled
 148   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 149   dsb
 150   isb
 151   bx      LR
 152
 153 ArmDisableDataCache
 154   ldr     R1,=DC_ON             ; Specify SCTLR.C bit : (Data) Cache enable bit
 155   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 156   bic     R0,R0,R1              ; Clear SCTLR.C bit : Data and unified caches disabled
 157   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 158   isb
 159   bx      LR
 160
 161 ArmEnableInstructionCache
 162   ldr     R1,=IC_ON             ; Specify SCTLR.I bit : Instruction cache enable bit
 163   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 164   orr     R0,R0,R1              ; Set SCTLR.I bit : Instruction caches enabled
 165   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 166   dsb
 167   isb
 168   bx      LR
 169
 170 ArmDisableInstructionCache
 171   ldr     R1,=IC_ON             ; Specify SCTLR.I bit : Instruction cache enable bit
 172   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 173   BIC     R0,R0,R1              ; Clear SCTLR.I bit : Instruction caches disabled
 174   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 175   isb
 176   bx      LR
 177
 178 ArmEnableSWPInstruction
 179   mrc     p15, 0, r0, c1, c0, 0
 180   orr     r0, r0, #0x00000400
 181   mcr     p15, 0, r0, c1, c0, 0
 182   isb
 183   bx      LR
 184
 185 ArmEnableBranchPrediction
 186   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 187   orr     r0, r0, #0x00000800   ;
 188   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 189   isb
 190   bx      LR
 191
 192 ArmDisableBranchPrediction
 193   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 194   bic     r0, r0, #0x00000800   ;
 195   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 196   isb
 197   bx      LR
 198
 199
 200 ArmV7AllDataCachesOperation
 201   stmfd SP!,{r4-r12, LR}
 202   mov   R1, R0                ; Save Function call in R1
 203   mrc   p15, 1, R6, c0, c0, 1 ; Read CLIDR
 204   ands  R3, R6, #&7000000     ; Mask out all but Level of Coherency (LoC)
 205   mov   R3, R3, LSR #23       ; Cache level value (naturally aligned)
 206   beq   Finished
 207   mov   R10, #0
 208
 209 Loop1
 210   add   R2, R10, R10, LSR #1    ; Work out 3xcachelevel
 211   mov   R12, R6, LSR R2         ; bottom 3 bits are the Cache type for this level
 212   and   R12, R12, #7            ; get those 3 bits alone
 213   cmp   R12, #2
 214   blt   Skip                    ; no cache or only instruction cache at this level
 215   mcr   p15, 2, R10, c0, c0, 0  ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
 216   isb                           ; isb to sync the change to the CacheSizeID reg
 217   mrc   p15, 1, R12, c0, c0, 0  ; reads current Cache Size ID register (CCSIDR)
 218   and   R2, R12, #&7            ; extract the line length field
 219   add   R2, R2, #4              ; add 4 for the line length offset (log2 16 bytes)
 220   ldr   R4, =0x3FF
 221   ands  R4, R4, R12, LSR #3     ; R4 is the max number on the way size (right aligned)
 222   clz   R5, R4                  ; R5 is the bit position of the way size increment
 223   ldr   R7, =0x00007FFF
 224   ands  R7, R7, R12, LSR #13    ; R7 is the max number of the index size (right aligned)
 225
 226 Loop2
 227   mov   R9, R4                  ; R9 working copy of the max way size (right aligned)
 228
 229 Loop3
 230   orr   R0, R10, R9, LSL R5     ; factor in the way number and cache number into R11
 231   orr   R0, R0, R7, LSL R2      ; factor in the index number
 232
 233   blx   R1
 234
 235   subs  R9, R9, #1              ; decrement the way number
 236   bge   Loop3
 237   subs  R7, R7, #1              ; decrement the index
 238   bge   Loop2
 239 Skip
 240   add   R10, R10, #2            ; increment the cache number
 241   cmp   R3, R10
 242   bgt   Loop1
 243
 244 Finished
 245   dsb
 246   ldmfd SP!, {r4-r12, lr}
 247   bx    LR
 248
 249
 250 ArmDataMemoryBarrier
 251   dmb
 252   bx      LR
 253
 254 ArmDataSyncronizationBarrier
 255 ArmDrainWriteBuffer
 256   dsb
 257   bx      LR
 258
 259 ArmInstructionSynchronizationBarrier
 260   isb
 261   bx      LR
 262
 263 ArmWriteNsacr
 264   mcr     p15, 0, r0, c1, c1, 2
 265   bx      lr
 266
 267 ArmWriteScr
 268   mcr     p15, 0, r0, c1, c1, 0
 269   bx      lr
 270
 271 ArmWriteAuxCr
 272   mcr     p15, 0, r0, c1, c0, 1
 273   bx      lr
 274
 275 ArmReadAuxCr
 276   mrc     p15, 0, r0, c1, c0, 1
 277   bx      lr
 278
 279 ArmWriteVMBar
 280   mcr     p15, 0, r0, c12, c0, 1
 281   bx      lr
 282
 283 ArmWriteVBar
 284   mcr     p15, 0, r0, c12, c0, 0
 285   bx      lr
 286
 287 ArmReadVBar
 288   mrc     p15, 0, r0, c12, c0, 0
 289   bx      lr
 290
 291 ArmWriteCPACR
 292   mcr     p15, 0, r0, c1, c0, 2
 293   bx      lr
 294
 295 ArmEnableVFP
 296   // Enable VFP registers
 297   mrc     p15, 0, r0, c1, c0, 2
 298   orr     r0, r0, #0x00f00000   // Enable VPF access (V* instructions)
 299   mcr     p15, 0, r0, c1, c0, 2
 300   mov     r0, #0x40000000       // Set EN bit in FPEXC
 301   mcr     p10,#0x7,r0,c8,c0,#0  // msr     FPEXC,r0 in ARM assembly
 302   bx      lr
 303
 304 ArmCallWFI
 305   wfi
 306   bx      lr
 307
 308 //Note: Return 0 in Uniprocessor implementation
 309 ArmReadCbar
 310   mrc     p15, 4, r0, c15, c0, 0\s\s//Read Configuration Base Address Register
 311   bx      lr
 312
 313 ArmInvalidateInstructionAndDataTlb
 314   mcr     p15, 0, r0, c8, c7, 0      ; Invalidate Inst TLB and Data TLB
 315   dsb
 316   bx lr
 317
 318 ArmReadMpidr
 319   mrc     p15, 0, r0, c0, c0, 5\s\s\s\s; read MPIDR
 320   bx      lr
 321
 322   END
 323