ArmPkg: ArmLib: purge incorrect ArmDrainWriteBuffer () alias
[mirror_edk2.git] / ArmPkg / Library / ArmLib / ArmV7 / ArmV7Support.asm
1 //------------------------------------------------------------------------------
2 //
3 // Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
4 // Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
5 //
6 // This program and the accompanying materials
7 // are licensed and made available under the terms and conditions of the BSD License
8 // which accompanies this distribution. The full text of the license may be found at
9 // http://opensource.org/licenses/bsd-license.php
10 //
11 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 //
14 //------------------------------------------------------------------------------
15
16 EXPORT ArmInvalidateInstructionCache
17 EXPORT ArmInvalidateDataCacheEntryByMVA
18 EXPORT ArmCleanDataCacheEntryByMVA
19 EXPORT ArmCleanInvalidateDataCacheEntryByMVA
20 EXPORT ArmInvalidateDataCacheEntryBySetWay
21 EXPORT ArmCleanDataCacheEntryBySetWay
22 EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
23 EXPORT ArmEnableMmu
24 EXPORT ArmDisableMmu
25 EXPORT ArmDisableCachesAndMmu
26 EXPORT ArmMmuEnabled
27 EXPORT ArmEnableDataCache
28 EXPORT ArmDisableDataCache
29 EXPORT ArmEnableInstructionCache
30 EXPORT ArmDisableInstructionCache
31 EXPORT ArmEnableSWPInstruction
32 EXPORT ArmEnableBranchPrediction
33 EXPORT ArmDisableBranchPrediction
34 EXPORT ArmSetLowVectors
35 EXPORT ArmSetHighVectors
36 EXPORT ArmV7AllDataCachesOperation
37 EXPORT ArmDataMemoryBarrier
38 EXPORT ArmDataSynchronizationBarrier
39 EXPORT ArmInstructionSynchronizationBarrier
40 EXPORT ArmReadVBar
41 EXPORT ArmWriteVBar
42 EXPORT ArmEnableVFP
43 EXPORT ArmCallWFI
44 EXPORT ArmReadCbar
45 EXPORT ArmReadMpidr
46 EXPORT ArmReadTpidrurw
47 EXPORT ArmWriteTpidrurw
48 EXPORT ArmIsArchTimerImplemented
49 EXPORT ArmReadIdPfr1
50 EXPORT ArmReadIdMmfr0
51
52 AREA ArmV7Support, CODE, READONLY
53 PRESERVE8
54
55 DC_ON EQU ( 0x1:SHL:2 )
56 IC_ON EQU ( 0x1:SHL:12 )
57 CTRL_M_BIT EQU (1 << 0)
58 CTRL_C_BIT EQU (1 << 2)
59 CTRL_B_BIT EQU (1 << 7)
60 CTRL_I_BIT EQU (1 << 12)
61
62
63 ArmInvalidateDataCacheEntryByMVA
64 mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
65 bx lr
66
67 ArmCleanDataCacheEntryByMVA
68 mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
69 bx lr
70
71
72 ArmCleanInvalidateDataCacheEntryByMVA
73 mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
74 bx lr
75
76
77 ArmInvalidateDataCacheEntryBySetWay
78 mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
79 bx lr
80
81
82 ArmCleanInvalidateDataCacheEntryBySetWay
83 mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
84 bx lr
85
86
87 ArmCleanDataCacheEntryBySetWay
88 mcr p15, 0, r0, c7, c10, 2 ; Clean this line
89 bx lr
90
91
92 ArmInvalidateInstructionCache
93 mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
94 isb
95 bx LR
96
97 ArmEnableMmu
98 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
99 orr R0,R0,#1 ; Set SCTLR.M bit : Enable MMU
100 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
101 dsb
102 isb
103 bx LR
104
105 ArmDisableMmu
106 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
107 bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU
108 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
109
110 mcr p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB
111 mcr p15,0,R0,c7,c5,6 ; BPIALL : Invalidate entire branch predictor array
112 dsb
113 isb
114 bx LR
115
116 ArmDisableCachesAndMmu
117 mrc p15, 0, r0, c1, c0, 0 ; Get control register
118 bic r0, r0, #CTRL_M_BIT ; Disable MMU
119 bic r0, r0, #CTRL_C_BIT ; Disable D Cache
120 bic r0, r0, #CTRL_I_BIT ; Disable I Cache
121 mcr p15, 0, r0, c1, c0, 0 ; Write control register
122 dsb
123 isb
124 bx LR
125
126 ArmMmuEnabled
127 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
128 and R0,R0,#1
129 bx LR
130
131 ArmEnableDataCache
132 ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
133 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
134 orr R0,R0,R1 ; Set SCTLR.C bit : Data and unified caches enabled
135 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
136 dsb
137 isb
138 bx LR
139
140 ArmDisableDataCache
141 ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
142 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
143 bic R0,R0,R1 ; Clear SCTLR.C bit : Data and unified caches disabled
144 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
145 dsb
146 isb
147 bx LR
148
149 ArmEnableInstructionCache
150 ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit
151 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
152 orr R0,R0,R1 ; Set SCTLR.I bit : Instruction caches enabled
153 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
154 dsb
155 isb
156 bx LR
157
158 ArmDisableInstructionCache
159 ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit
160 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
161 BIC R0,R0,R1 ; Clear SCTLR.I bit : Instruction caches disabled
162 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
163 isb
164 bx LR
165
166 ArmEnableSWPInstruction
167 mrc p15, 0, r0, c1, c0, 0
168 orr r0, r0, #0x00000400
169 mcr p15, 0, r0, c1, c0, 0
170 isb
171 bx LR
172
173 ArmEnableBranchPrediction
174 mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
175 orr r0, r0, #0x00000800 ;
176 mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
177 dsb
178 isb
179 bx LR
180
181 ArmDisableBranchPrediction
182 mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
183 bic r0, r0, #0x00000800 ;
184 mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
185 dsb
186 isb
187 bx LR
188
189 ArmSetLowVectors
190 mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
191 bic r0, r0, #0x00002000 ; clear V bit
192 mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
193 isb
194 bx LR
195
196 ArmSetHighVectors
197 mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
198 orr r0, r0, #0x00002000 ; Set V bit
199 mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
200 isb
201 bx LR
202
203 ArmV7AllDataCachesOperation
204 stmfd SP!,{r4-r12, LR}
205 mov R1, R0 ; Save Function call in R1
206 mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR
207 ands R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC)
208 mov R3, R3, LSR #23 ; Cache level value (naturally aligned)
209 beq Finished
210 mov R10, #0
211
212 Loop1
213 add R2, R10, R10, LSR #1 ; Work out 3xcachelevel
214 mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level
215 and R12, R12, #7 ; get those 3 bits alone
216 cmp R12, #2
217 blt Skip ; no cache or only instruction cache at this level
218 mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
219 isb ; isb to sync the change to the CacheSizeID reg
220 mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)
221 and R2, R12, #&7 ; extract the line length field
222 add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)
223 ldr R4, =0x3FF
224 ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)
225 clz R5, R4 ; R5 is the bit position of the way size increment
226 ldr R7, =0x00007FFF
227 ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)
228
229 Loop2
230 mov R9, R4 ; R9 working copy of the max way size (right aligned)
231
232 Loop3
233 orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11
234 orr R0, R0, R7, LSL R2 ; factor in the index number
235
236 blx R1
237
238 subs R9, R9, #1 ; decrement the way number
239 bge Loop3
240 subs R7, R7, #1 ; decrement the index
241 bge Loop2
242 Skip
243 add R10, R10, #2 ; increment the cache number
244 cmp R3, R10
245 bgt Loop1
246
247 Finished
248 dsb
249 ldmfd SP!, {r4-r12, lr}
250 bx LR
251
252 ArmDataMemoryBarrier
253 dmb
254 bx LR
255
256 ArmDataSynchronizationBarrier
257 dsb
258 bx LR
259
260 ArmInstructionSynchronizationBarrier
261 isb
262 bx LR
263
264 ArmReadVBar
265 // Set the Address of the Vector Table in the VBAR register
266 mrc p15, 0, r0, c12, c0, 0
267 bx lr
268
269 ArmWriteVBar
270 // Set the Address of the Vector Table in the VBAR register
271 mcr p15, 0, r0, c12, c0, 0
272 // Ensure the SCTLR.V bit is clear
273 mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
274 bic r0, r0, #0x00002000 ; clear V bit
275 mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
276 isb
277 bx lr
278
279 ArmEnableVFP
280 // Read CPACR (Coprocessor Access Control Register)
281 mrc p15, 0, r0, c1, c0, 2
282 // Enable VPF access (Full Access to CP10, CP11) (V* instructions)
283 orr r0, r0, #0x00f00000
284 // Write back CPACR (Coprocessor Access Control Register)
285 mcr p15, 0, r0, c1, c0, 2
286 isb
287 // Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
288 mov r0, #0x40000000
289 mcr p10,#0x7,r0,c8,c0,#0
290 bx lr
291
292 ArmCallWFI
293 wfi
294 bx lr
295
296 //Note: Return 0 in Uniprocessor implementation
297 ArmReadCbar
298 mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register
299 bx lr
300
301 ArmReadMpidr
302 mrc p15, 0, r0, c0, c0, 5 ; read MPIDR
303 bx lr
304
305 ArmReadTpidrurw
306 mrc p15, 0, r0, c13, c0, 2 ; read TPIDRURW
307 bx lr
308
309 ArmWriteTpidrurw
310 mcr p15, 0, r0, c13, c0, 2 ; write TPIDRURW
311 bx lr
312
313 ArmIsArchTimerImplemented
314 mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1
315 and r0, r0, #0x000F0000
316 bx lr
317
318 ArmReadIdPfr1
319 mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1 Register
320 bx lr
321
322 ArmReadIdMmfr0
323 mrc p15, 0, r0, c0, c1, 4 ; Read ID_MMFR0 Register
324 bx lr
325
326 END