ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm

   1 //------------------------------------------------------------------------------
   2 //
   3 // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4 //
   5 // This program and the accompanying materials
   6 // are licensed and made available under the terms and conditions of the BSD License
   7 // which accompanies this distribution.  The full text of the license may be found at
   8 // http://opensource.org/licenses/bsd-license.php
   9 //
  10 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 //
  13 //------------------------------------------------------------------------------
  14
  15     EXPORT  ArmInvalidateInstructionCache
  16     EXPORT  ArmInvalidateDataCacheEntryByMVA
  17     EXPORT  ArmCleanDataCacheEntryByMVA
  18     EXPORT  ArmCleanInvalidateDataCacheEntryByMVA
  19     EXPORT  ArmInvalidateDataCacheEntryBySetWay
  20     EXPORT  ArmCleanDataCacheEntryBySetWay
  21     EXPORT  ArmCleanInvalidateDataCacheEntryBySetWay
  22     EXPORT  ArmDrainWriteBuffer
  23     EXPORT  ArmEnableMmu
  24     EXPORT  ArmDisableMmu
  25     EXPORT  ArmDisableCachesAndMmu
  26     EXPORT  ArmMmuEnabled
  27     EXPORT  ArmEnableDataCache
  28     EXPORT  ArmDisableDataCache
  29     EXPORT  ArmEnableInstructionCache
  30     EXPORT  ArmDisableInstructionCache
  31     EXPORT  ArmEnableSWPInstruction
  32     EXPORT  ArmEnableBranchPrediction
  33     EXPORT  ArmDisableBranchPrediction
  34     EXPORT  ArmSetLowVectors
  35     EXPORT  ArmSetHighVectors
  36     EXPORT  ArmV7AllDataCachesOperation
  37     EXPORT  ArmDataMemoryBarrier
  38     EXPORT  ArmDataSyncronizationBarrier
  39     EXPORT  ArmInstructionSynchronizationBarrier
  40     EXPORT  ArmWriteNsacr
  41     EXPORT  ArmWriteScr
  42     EXPORT  ArmWriteVMBar
  43     EXPORT  ArmWriteVBar
  44     EXPORT  ArmReadVBar
  45     EXPORT  ArmWriteCPACR
  46     EXPORT  ArmEnableVFP
  47     EXPORT  ArmCallWFI
  48     EXPORT  ArmWriteAuxCr
  49     EXPORT  ArmReadAuxCr
  50     EXPORT  ArmReadCbar
  51     EXPORT  ArmInvalidateInstructionAndDataTlb
  52     EXPORT  ArmReadMpidr
  53     EXPORT  ArmReadTpidrurw
  54     EXPORT  ArmWriteTpidrurw
  55
  56     AREA    ArmCacheLib, CODE, READONLY
  57     PRESERVE8
  58
  59 DC_ON           EQU     ( 0x1:SHL:2 )
  60 IC_ON           EQU     ( 0x1:SHL:12 )
  61 CTRL_M_BIT      EQU     (1 << 0)
  62 CTRL_C_BIT      EQU     (1 << 2)
  63 CTRL_B_BIT      EQU     (1 << 7)
  64 CTRL_I_BIT      EQU     (1 << 12)
  65
  66
  67 ArmInvalidateDataCacheEntryByMVA
  68   mcr     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line
  69   dsb
  70   isb
  71   bx      lr
  72
  73
  74 ArmCleanDataCacheEntryByMVA
  75   mcr     p15, 0, r0, c7, c10, 1  ; clean single data cache line
  76   dsb
  77   isb
  78   bx      lr
  79
  80
  81 ArmCleanInvalidateDataCacheEntryByMVA
  82   mcr     p15, 0, r0, c7, c14, 1  ; clean and invalidate single data cache line
  83   dsb
  84   isb
  85   bx      lr
  86
  87
  88 ArmInvalidateDataCacheEntryBySetWay
  89   mcr     p15, 0, r0, c7, c6, 2        ; Invalidate this line
  90   dsb
  91   isb
  92   bx      lr
  93
  94
  95 ArmCleanInvalidateDataCacheEntryBySetWay
  96   mcr     p15, 0, r0, c7, c14, 2       ; Clean and Invalidate this line
  97   dsb
  98   isb
  99   bx      lr
 100
 101
 102 ArmCleanDataCacheEntryBySetWay
 103   mcr     p15, 0, r0, c7, c10, 2       ; Clean this line
 104   dsb
 105   isb
 106   bx      lr
 107
 108
 109 ArmInvalidateInstructionCache
 110   mcr     p15,0,R0,c7,c5,0      ;Invalidate entire instruction cache
 111   isb
 112   bx      LR
 113
 114 ArmEnableMmu
 115   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 116   orr     R0,R0,#1              ; Set SCTLR.M bit : Enable MMU
 117   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 118   dsb
 119   isb
 120   bx      LR
 121
 122 ArmMmuEnabled
 123   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 124   and     R0,R0,#1
 125   bx      LR
 126
 127 ArmDisableMmu
 128   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 129   bic     R0,R0,#1              ; Clear SCTLR.M bit : Disable MMU
 130   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 131
 132   mcr     p15,0,R0,c8,c7,0      ; TLBIALL : Invalidate unified TLB
 133   mcr     p15,0,R0,c7,c5,6      ; BPIALL  : Invalidate entire branch predictor array
 134   dsb
 135   isb
 136   bx      LR
 137
 138 ArmDisableCachesAndMmu
 139   mrc   p15, 0, r0, c1, c0, 0           ; Get control register
 140   bic   r0, r0, #CTRL_M_BIT             ; Disable MMU
 141   bic   r0, r0, #CTRL_C_BIT             ; Disable D Cache
 142   bic   r0, r0, #CTRL_I_BIT             ; Disable I Cache
 143   mcr   p15, 0, r0, c1, c0, 0           ; Write control register
 144   dsb
 145   isb
 146   bx      LR
 147
 148 ArmEnableDataCache
 149   ldr     R1,=DC_ON             ; Specify SCTLR.C bit : (Data) Cache enable bit
 150   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 151   orr     R0,R0,R1              ; Set SCTLR.C bit : Data and unified caches enabled
 152   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 153   dsb
 154   isb
 155   bx      LR
 156
 157 ArmDisableDataCache
 158   ldr     R1,=DC_ON             ; Specify SCTLR.C bit : (Data) Cache enable bit
 159   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 160   bic     R0,R0,R1              ; Clear SCTLR.C bit : Data and unified caches disabled
 161   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 162   isb
 163   bx      LR
 164
 165 ArmEnableInstructionCache
 166   ldr     R1,=IC_ON             ; Specify SCTLR.I bit : Instruction cache enable bit
 167   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 168   orr     R0,R0,R1              ; Set SCTLR.I bit : Instruction caches enabled
 169   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 170   dsb
 171   isb
 172   bx      LR
 173
 174 ArmDisableInstructionCache
 175   ldr     R1,=IC_ON             ; Specify SCTLR.I bit : Instruction cache enable bit
 176   mrc     p15,0,R0,c1,c0,0      ; Read SCTLR into R0 (Read control register configuration data)
 177   BIC     R0,R0,R1              ; Clear SCTLR.I bit : Instruction caches disabled
 178   mcr     p15,0,R0,c1,c0,0      ; Write R0 into SCTLR (Write control register configuration data)
 179   isb
 180   bx      LR
 181
 182 ArmEnableSWPInstruction
 183   mrc     p15, 0, r0, c1, c0, 0
 184   orr     r0, r0, #0x00000400
 185   mcr     p15, 0, r0, c1, c0, 0
 186   isb
 187   bx      LR
 188
 189 ArmEnableBranchPrediction
 190   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 191   orr     r0, r0, #0x00000800   ;
 192   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 193   isb
 194   bx      LR
 195
 196 ArmDisableBranchPrediction
 197   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 198   bic     r0, r0, #0x00000800   ;
 199   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 200   isb
 201   bx      LR
 202
 203 ArmSetLowVectors
 204   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 205   bic     r0, r0, #0x00002000   ; clear V bit
 206   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 207   isb
 208   bx      LR
 209
 210 ArmSetHighVectors
 211   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 212   orr     r0, r0, #0x00002000   ; clear V bit
 213   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 214   isb
 215   bx      LR
 216
 217 ArmV7AllDataCachesOperation
 218   stmfd SP!,{r4-r12, LR}
 219   mov   R1, R0                ; Save Function call in R1
 220   mrc   p15, 1, R6, c0, c0, 1 ; Read CLIDR
 221   ands  R3, R6, #&7000000     ; Mask out all but Level of Coherency (LoC)
 222   mov   R3, R3, LSR #23       ; Cache level value (naturally aligned)
 223   beq   Finished
 224   mov   R10, #0
 225
 226 Loop1
 227   add   R2, R10, R10, LSR #1    ; Work out 3xcachelevel
 228   mov   R12, R6, LSR R2         ; bottom 3 bits are the Cache type for this level
 229   and   R12, R12, #7            ; get those 3 bits alone
 230   cmp   R12, #2
 231   blt   Skip                    ; no cache or only instruction cache at this level
 232   mcr   p15, 2, R10, c0, c0, 0  ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
 233   isb                           ; isb to sync the change to the CacheSizeID reg
 234   mrc   p15, 1, R12, c0, c0, 0  ; reads current Cache Size ID register (CCSIDR)
 235   and   R2, R12, #&7            ; extract the line length field
 236   add   R2, R2, #4              ; add 4 for the line length offset (log2 16 bytes)
 237   ldr   R4, =0x3FF
 238   ands  R4, R4, R12, LSR #3     ; R4 is the max number on the way size (right aligned)
 239   clz   R5, R4                  ; R5 is the bit position of the way size increment
 240   ldr   R7, =0x00007FFF
 241   ands  R7, R7, R12, LSR #13    ; R7 is the max number of the index size (right aligned)
 242
 243 Loop2
 244   mov   R9, R4                  ; R9 working copy of the max way size (right aligned)
 245
 246 Loop3
 247   orr   R0, R10, R9, LSL R5     ; factor in the way number and cache number into R11
 248   orr   R0, R0, R7, LSL R2      ; factor in the index number
 249
 250   blx   R1
 251
 252   subs  R9, R9, #1              ; decrement the way number
 253   bge   Loop3
 254   subs  R7, R7, #1              ; decrement the index
 255   bge   Loop2
 256 Skip
 257   add   R10, R10, #2            ; increment the cache number
 258   cmp   R3, R10
 259   bgt   Loop1
 260
 261 Finished
 262   dsb
 263   ldmfd SP!, {r4-r12, lr}
 264   bx    LR
 265
 266
 267 ArmDataMemoryBarrier
 268   dmb
 269   bx      LR
 270
 271 ArmDataSyncronizationBarrier
 272 ArmDrainWriteBuffer
 273   dsb
 274   bx      LR
 275
 276 ArmInstructionSynchronizationBarrier
 277   isb
 278   bx      LR
 279
 280 ArmWriteNsacr
 281   mcr     p15, 0, r0, c1, c1, 2
 282   bx      lr
 283
 284 ArmWriteScr
 285   mcr     p15, 0, r0, c1, c1, 0
 286   bx      lr
 287
 288 ArmWriteAuxCr
 289   mcr     p15, 0, r0, c1, c0, 1
 290   bx      lr
 291
 292 ArmReadAuxCr
 293   mrc     p15, 0, r0, c1, c0, 1
 294   bx      lr
 295
 296 ArmWriteVMBar
 297   mcr     p15, 0, r0, c12, c0, 1
 298   bx      lr
 299
 300 ArmWriteVBar
 301   // Set the Address of the Vector Table in the VBAR register
 302   mcr     p15, 0, r0, c12, c0, 0
 303   // Ensure the SCTLR.V bit is clear
 304   mrc     p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
 305   bic     r0, r0, #0x00002000   ; clear V bit
 306   mcr     p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
 307   isb
 308   bx      lr
 309
 310 ArmReadVBar
 311   mrc     p15, 0, r0, c12, c0, 0
 312   bx      lr
 313
 314 ArmWriteCPACR
 315   mcr     p15, 0, r0, c1, c0, 2
 316   bx      lr
 317
 318 ArmEnableVFP
 319   // Read CPACR (Coprocessor Access Control Register)
 320   mrc     p15, 0, r0, c1, c0, 2
 321   // Enable VPF access (Full Access to CP10, CP11) (V* instructions)
 322   orr     r0, r0, #0x00f00000
 323   // Write back CPACR (Coprocessor Access Control Register)
 324   mcr     p15, 0, r0, c1, c0, 2
 325   // Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
 326   mov     r0, #0x40000000
 327   mcr     p10,#0x7,r0,c8,c0,#0
 328   bx      lr
 329
 330 ArmCallWFI
 331   wfi
 332   bx      lr
 333
 334 //Note: Return 0 in Uniprocessor implementation
 335 ArmReadCbar
 336   mrc     p15, 4, r0, c15, c0, 0  //Read Configuration Base Address Register
 337   bx      lr
 338
 339 ArmInvalidateInstructionAndDataTlb
 340   mcr     p15, 0, r0, c8, c7, 0      ; Invalidate Inst TLB and Data TLB
 341   dsb
 342   bx lr
 343
 344 ArmReadMpidr
 345   mrc     p15, 0, r0, c0, c0, 5    ; read MPIDR
 346   bx      lr
 347
 348 ArmReadTpidrurw
 349   mrc     p15, 0, r0, c13, c0, 2    ; read TPIDRURW
 350   bx      lr
 351
 352 ArmWriteTpidrurw
 353   mcr     p15, 0, r0, c13, c0, 2    ; write TPIDRURW
 354   bx      lr
 355
 356   END
 357