1 //------------------------------------------------------------------------------
3 // Copyright (c) 2008-2009 Apple Inc. All rights reserved.
5 // All rights reserved. This program and the accompanying materials
6 // are licensed and made available under the terms and conditions of the BSD License
7 // which accompanies this distribution. The full text of the license may be found at
8 // http://opensource.org/licenses/bsd-license.php
10 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 //------------------------------------------------------------------------------
15 EXPORT ArmInvalidateInstructionCache
16 EXPORT ArmInvalidateDataCacheEntryByMVA
17 EXPORT ArmCleanDataCacheEntryByMVA
18 EXPORT ArmCleanInvalidateDataCacheEntryByMVA
19 EXPORT ArmInvalidateDataCacheEntryBySetWay
20 EXPORT ArmCleanDataCacheEntryBySetWay
21 EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
22 EXPORT ArmDrainWriteBuffer
26 EXPORT ArmEnableDataCache
27 EXPORT ArmDisableDataCache
28 EXPORT ArmEnableInstructionCache
29 EXPORT ArmDisableInstructionCache
30 EXPORT ArmEnableBranchPrediction
31 EXPORT ArmDisableBranchPrediction
32 EXPORT ArmV7AllDataCachesOperation
33 EXPORT ArmDataMemoryBarrier
34 EXPORT ArmDataSyncronizationBarrier
35 EXPORT ArmInstructionSynchronizationBarrier
37 AREA ArmCacheLib, CODE, READONLY
40 DC_ON EQU ( 0x1:SHL:2 )
41 IC_ON EQU ( 0x1:SHL:12 )
45 ArmInvalidateDataCacheEntryByMVA
46 mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
52 ArmCleanDataCacheEntryByMVA
53 mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
59 ArmCleanInvalidateDataCacheEntryByMVA
60 mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
66 ArmInvalidateDataCacheEntryBySetWay
67 mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
73 ArmCleanInvalidateDataCacheEntryBySetWay
74 mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
80 ArmCleanDataCacheEntryBySetWay
81 mcr p15, 0, r0, c7, c10, 2 ; Clean this line
87 ArmInvalidateInstructionCache
88 mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
109 mcr p15,0,R0,c1,c0,0 ;Disable MMU
111 mcr p15,0,R0,c8,c7,0 ;Invalidate TLB
112 mcr p15,0,R0,c7,c5,6 ;Invalidate Branch predictor array
120 mrc p15,0,R0,c1,c0,0 ;Read control register configuration data
121 orr R0,R0,R1 ;Set C bit
122 mcr p15,0,R0,c1,c0,0 ;Write control register configuration data
129 mrc p15,0,R0,c1,c0,0 ;Read control register configuration data
130 bic R0,R0,R1 ;Clear C bit
131 mcr p15,0,R0,c1,c0,0 ;Write control register configuration data
135 ArmEnableInstructionCache
137 mrc p15,0,R0,c1,c0,0 ;Read control register configuration data
138 orr R0,R0,R1 ;Set I bit
139 mcr p15,0,R0,c1,c0,0 ;Write control register configuration data
144 ArmDisableInstructionCache
146 mrc p15,0,R0,c1,c0,0 ;Read control register configuration data
147 BIC R0,R0,R1 ;Clear I bit.
148 mcr p15,0,R0,c1,c0,0 ;Write control register configuration data
152 ArmEnableBranchPrediction
153 mrc p15, 0, r0, c1, c0, 0
154 orr r0, r0, #0x00000800
155 mcr p15, 0, r0, c1, c0, 0
159 ArmDisableBranchPrediction
160 mrc p15, 0, r0, c1, c0, 0
161 bic r0, r0, #0x00000800
162 mcr p15, 0, r0, c1, c0, 0
167 ArmV7AllDataCachesOperation
168 stmfd SP!,{r4-r12, LR}
169 mov R1, R0 ; Save Function call in R1
170 mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR
171 ands R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC)
172 mov R3, R3, LSR #23 ; Cache level value (naturally aligned)
177 add R2, R10, R10, LSR #1 ; Work out 3xcachelevel
178 mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level
179 and R12, R12, #7 ; get those 3 bits alone
181 blt Skip ; no cache or only instruction cache at this level
182 mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
183 isb ; isb to sync the change to the CacheSizeID reg
184 mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)
185 and R2, R12, #&7 ; extract the line length field
186 add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)
188 ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)
189 clz R5, R4 ; R5 is the bit position of the way size increment
191 ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)
194 mov R9, R4 ; R9 working copy of the max way size (right aligned)
197 orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11
198 orr R0, R0, R7, LSL R2 ; factor in the index number
202 subs R9, R9, #1 ; decrement the way number
204 subs R7, R7, #1 ; decrement the index
207 add R10, R10, #2 ; increment the cache number
213 ldmfd SP!, {r4-r12, lr}
221 ArmDataSyncronizationBarrier
226 ArmInstructionSynchronizationBarrier