64c820725177871ca89c79ff1fc3fcda685405ad
[mirror_edk2.git] / ArmPkg / Library / ArmLib / ArmV7 / ArmV7Support.asm
1 //------------------------------------------------------------------------------
2 //
3 // Copyright (c) 2008-2009 Apple Inc. All rights reserved.
4 //
5 // All rights reserved. This program and the accompanying materials
6 // are licensed and made available under the terms and conditions of the BSD License
7 // which accompanies this distribution. The full text of the license may be found at
8 // http://opensource.org/licenses/bsd-license.php
9 //
10 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12 //
13 //------------------------------------------------------------------------------
14
15 EXPORT ArmInvalidateInstructionCache
16 EXPORT ArmInvalidateDataCacheEntryByMVA
17 EXPORT ArmCleanDataCacheEntryByMVA
18 EXPORT ArmCleanInvalidateDataCacheEntryByMVA
19 EXPORT ArmInvalidateDataCacheEntryBySetWay
20 EXPORT ArmCleanDataCacheEntryBySetWay
21 EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
22 EXPORT ArmDrainWriteBuffer
23 EXPORT ArmEnableMmu
24 EXPORT ArmDisableMmu
25 EXPORT ArmMmuEnabled
26 EXPORT ArmEnableDataCache
27 EXPORT ArmDisableDataCache
28 EXPORT ArmEnableInstructionCache
29 EXPORT ArmDisableInstructionCache
30 EXPORT ArmEnableBranchPrediction
31 EXPORT ArmDisableBranchPrediction
32 EXPORT ArmV7AllDataCachesOperation
33 EXPORT ArmDataMemoryBarrier
34 EXPORT ArmDataSyncronizationBarrier
35 EXPORT ArmInstructionSynchronizationBarrier
36
37 AREA ArmCacheLib, CODE, READONLY
38 PRESERVE8
39
40 DC_ON EQU ( 0x1:SHL:2 )
41 IC_ON EQU ( 0x1:SHL:12 )
42
43
44
45 ArmInvalidateDataCacheEntryByMVA
46 mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
47 dsb
48 isb
49 bx lr
50
51
52 ArmCleanDataCacheEntryByMVA
53 mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
54 dsb
55 isb
56 bx lr
57
58
59 ArmCleanInvalidateDataCacheEntryByMVA
60 mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
61 dsb
62 isb
63 bx lr
64
65
66 ArmInvalidateDataCacheEntryBySetWay
67 mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
68 dsb
69 isb
70 bx lr
71
72
73 ArmCleanInvalidateDataCacheEntryBySetWay
74 mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
75 dsb
76 isb
77 bx lr
78
79
80 ArmCleanDataCacheEntryBySetWay
81 mcr p15, 0, r0, c7, c10, 2 ; Clean this line
82 dsb
83 isb
84 bx lr
85
86
87 ArmInvalidateInstructionCache
88 mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
89 dsb
90 isb
91 bx LR
92
93 ArmEnableMmu
94 mrc p15,0,R0,c1,c0,0
95 orr R0,R0,#1
96 mcr p15,0,R0,c1,c0,0
97 dsb
98 isb
99 bx LR
100
101 ArmMmuEnabled
102 mrc p15,0,R0,c1,c0,0
103 and R0,R0,#1
104 bx LR
105
106 ArmDisableMmu
107 mrc p15,0,R0,c1,c0,0
108 bic R0,R0,#1
109 mcr p15,0,R0,c1,c0,0 ;Disable MMU
110
111 mcr p15,0,R0,c8,c7,0 ;Invalidate TLB
112 mcr p15,0,R0,c7,c5,6 ;Invalidate Branch predictor array
113 dsb
114 isb
115 bx LR
116
117
118 ArmEnableDataCache
119 ldr R1,=DC_ON
120 mrc p15,0,R0,c1,c0,0 ;Read control register configuration data
121 orr R0,R0,R1 ;Set C bit
122 mcr p15,0,R0,c1,c0,0 ;Write control register configuration data
123 dsb
124 isb
125 bx LR
126
127 ArmDisableDataCache
128 ldr R1,=DC_ON
129 mrc p15,0,R0,c1,c0,0 ;Read control register configuration data
130 bic R0,R0,R1 ;Clear C bit
131 mcr p15,0,R0,c1,c0,0 ;Write control register configuration data
132 isb
133 bx LR
134
135 ArmEnableInstructionCache
136 ldr R1,=IC_ON
137 mrc p15,0,R0,c1,c0,0 ;Read control register configuration data
138 orr R0,R0,R1 ;Set I bit
139 mcr p15,0,R0,c1,c0,0 ;Write control register configuration data
140 dsb
141 isb
142 bx LR
143
144 ArmDisableInstructionCache
145 ldr R1,=IC_ON
146 mrc p15,0,R0,c1,c0,0 ;Read control register configuration data
147 BIC R0,R0,R1 ;Clear I bit.
148 mcr p15,0,R0,c1,c0,0 ;Write control register configuration data
149 isb
150 bx LR
151
152 ArmEnableBranchPrediction
153 mrc p15, 0, r0, c1, c0, 0
154 orr r0, r0, #0x00000800
155 mcr p15, 0, r0, c1, c0, 0
156 isb
157 bx LR
158
159 ArmDisableBranchPrediction
160 mrc p15, 0, r0, c1, c0, 0
161 bic r0, r0, #0x00000800
162 mcr p15, 0, r0, c1, c0, 0
163 isb
164 bx LR
165
166
167 ArmV7AllDataCachesOperation
168 stmfd SP!,{r4-r12, LR}
169 mov R1, R0 ; Save Function call in R1
170 mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR
171 ands R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC)
172 mov R3, R3, LSR #23 ; Cache level value (naturally aligned)
173 beq Finished
174 mov R10, #0
175
176 Loop1
177 add R2, R10, R10, LSR #1 ; Work out 3xcachelevel
178 mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level
179 and R12, R12, #7 ; get those 3 bits alone
180 cmp R12, #2
181 blt Skip ; no cache or only instruction cache at this level
182 mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
183 isb ; isb to sync the change to the CacheSizeID reg
184 mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)
185 and R2, R12, #&7 ; extract the line length field
186 add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)
187 ldr R4, =0x3FF
188 ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)
189 clz R5, R4 ; R5 is the bit position of the way size increment
190 ldr R7, =0x00007FFF
191 ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)
192
193 Loop2
194 mov R9, R4 ; R9 working copy of the max way size (right aligned)
195
196 Loop3
197 orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11
198 orr R0, R0, R7, LSL R2 ; factor in the index number
199
200 blx R1
201
202 subs R9, R9, #1 ; decrement the way number
203 bge Loop3
204 subs R7, R7, #1 ; decrement the index
205 bge Loop2
206 Skip
207 add R10, R10, #2 ; increment the cache number
208 cmp R3, R10
209 bgt Loop1
210
211 Finished
212 dsb
213 ldmfd SP!, {r4-r12, lr}
214 bx LR
215
216
217 ArmDataMemoryBarrier
218 dmb
219 bx LR
220
221 ArmDataSyncronizationBarrier
222 ArmDrainWriteBuffer
223 dsb
224 bx LR
225
226 ArmInstructionSynchronizationBarrier
227 isb
228 bx LR
229
230 END