78a12e1629b476918ad82400517707a4f5563dfb
[mirror_edk2.git] / ArmPkg / Library / ArmLib / ArmV7 / ArmV7Support.asm
1 //------------------------------------------------------------------------------
2 //
3 // Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
4 // Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
5 //
6 // This program and the accompanying materials
7 // are licensed and made available under the terms and conditions of the BSD License
8 // which accompanies this distribution. The full text of the license may be found at
9 // http://opensource.org/licenses/bsd-license.php
10 //
11 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 //
14 //------------------------------------------------------------------------------
15
16 EXPORT ArmInvalidateInstructionCache
17 EXPORT ArmInvalidateDataCacheEntryByMVA
18 EXPORT ArmCleanDataCacheEntryByMVA
19 EXPORT ArmCleanInvalidateDataCacheEntryByMVA
20 EXPORT ArmInvalidateDataCacheEntryBySetWay
21 EXPORT ArmCleanDataCacheEntryBySetWay
22 EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
23 EXPORT ArmDrainWriteBuffer
24 EXPORT ArmEnableMmu
25 EXPORT ArmDisableMmu
26 EXPORT ArmDisableCachesAndMmu
27 EXPORT ArmMmuEnabled
28 EXPORT ArmEnableDataCache
29 EXPORT ArmDisableDataCache
30 EXPORT ArmEnableInstructionCache
31 EXPORT ArmDisableInstructionCache
32 EXPORT ArmEnableSWPInstruction
33 EXPORT ArmEnableBranchPrediction
34 EXPORT ArmDisableBranchPrediction
35 EXPORT ArmSetLowVectors
36 EXPORT ArmSetHighVectors
37 EXPORT ArmV7AllDataCachesOperation
38 EXPORT ArmDataMemoryBarrier
39 EXPORT ArmDataSynchronizationBarrier
40 EXPORT ArmInstructionSynchronizationBarrier
41 EXPORT ArmReadVBar
42 EXPORT ArmWriteVBar
43 EXPORT ArmEnableVFP
44 EXPORT ArmCallWFI
45 EXPORT ArmReadCbar
46 EXPORT ArmReadMpidr
47 EXPORT ArmReadTpidrurw
48 EXPORT ArmWriteTpidrurw
49 EXPORT ArmIsArchTimerImplemented
50 EXPORT ArmReadIdPfr1
51 EXPORT ArmReadIdMmfr0
52
53 AREA ArmV7Support, CODE, READONLY
54 PRESERVE8
55
56 DC_ON EQU ( 0x1:SHL:2 )
57 IC_ON EQU ( 0x1:SHL:12 )
58 CTRL_M_BIT EQU (1 << 0)
59 CTRL_C_BIT EQU (1 << 2)
60 CTRL_B_BIT EQU (1 << 7)
61 CTRL_I_BIT EQU (1 << 12)
62
63
64 ArmInvalidateDataCacheEntryByMVA
65 mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
66 bx lr
67
68 ArmCleanDataCacheEntryByMVA
69 mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
70 bx lr
71
72
73 ArmCleanInvalidateDataCacheEntryByMVA
74 mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
75 bx lr
76
77
78 ArmInvalidateDataCacheEntryBySetWay
79 mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
80 bx lr
81
82
83 ArmCleanInvalidateDataCacheEntryBySetWay
84 mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
85 bx lr
86
87
88 ArmCleanDataCacheEntryBySetWay
89 mcr p15, 0, r0, c7, c10, 2 ; Clean this line
90 bx lr
91
92
93 ArmInvalidateInstructionCache
94 mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
95 isb
96 bx LR
97
98 ArmEnableMmu
99 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
100 orr R0,R0,#1 ; Set SCTLR.M bit : Enable MMU
101 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
102 dsb
103 isb
104 bx LR
105
106 ArmDisableMmu
107 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
108 bic R0,R0,#1 ; Clear SCTLR.M bit : Disable MMU
109 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
110
111 mcr p15,0,R0,c8,c7,0 ; TLBIALL : Invalidate unified TLB
112 mcr p15,0,R0,c7,c5,6 ; BPIALL : Invalidate entire branch predictor array
113 dsb
114 isb
115 bx LR
116
117 ArmDisableCachesAndMmu
118 mrc p15, 0, r0, c1, c0, 0 ; Get control register
119 bic r0, r0, #CTRL_M_BIT ; Disable MMU
120 bic r0, r0, #CTRL_C_BIT ; Disable D Cache
121 bic r0, r0, #CTRL_I_BIT ; Disable I Cache
122 mcr p15, 0, r0, c1, c0, 0 ; Write control register
123 dsb
124 isb
125 bx LR
126
127 ArmMmuEnabled
128 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
129 and R0,R0,#1
130 bx LR
131
132 ArmEnableDataCache
133 ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
134 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
135 orr R0,R0,R1 ; Set SCTLR.C bit : Data and unified caches enabled
136 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
137 dsb
138 isb
139 bx LR
140
141 ArmDisableDataCache
142 ldr R1,=DC_ON ; Specify SCTLR.C bit : (Data) Cache enable bit
143 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
144 bic R0,R0,R1 ; Clear SCTLR.C bit : Data and unified caches disabled
145 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
146 dsb
147 isb
148 bx LR
149
150 ArmEnableInstructionCache
151 ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit
152 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
153 orr R0,R0,R1 ; Set SCTLR.I bit : Instruction caches enabled
154 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
155 dsb
156 isb
157 bx LR
158
159 ArmDisableInstructionCache
160 ldr R1,=IC_ON ; Specify SCTLR.I bit : Instruction cache enable bit
161 mrc p15,0,R0,c1,c0,0 ; Read SCTLR into R0 (Read control register configuration data)
162 BIC R0,R0,R1 ; Clear SCTLR.I bit : Instruction caches disabled
163 mcr p15,0,R0,c1,c0,0 ; Write R0 into SCTLR (Write control register configuration data)
164 isb
165 bx LR
166
167 ArmEnableSWPInstruction
168 mrc p15, 0, r0, c1, c0, 0
169 orr r0, r0, #0x00000400
170 mcr p15, 0, r0, c1, c0, 0
171 isb
172 bx LR
173
174 ArmEnableBranchPrediction
175 mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
176 orr r0, r0, #0x00000800 ;
177 mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
178 dsb
179 isb
180 bx LR
181
182 ArmDisableBranchPrediction
183 mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
184 bic r0, r0, #0x00000800 ;
185 mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
186 dsb
187 isb
188 bx LR
189
190 ArmSetLowVectors
191 mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
192 bic r0, r0, #0x00002000 ; clear V bit
193 mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
194 isb
195 bx LR
196
197 ArmSetHighVectors
198 mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
199 orr r0, r0, #0x00002000 ; Set V bit
200 mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
201 isb
202 bx LR
203
204 ArmV7AllDataCachesOperation
205 stmfd SP!,{r4-r12, LR}
206 mov R1, R0 ; Save Function call in R1
207 mrc p15, 1, R6, c0, c0, 1 ; Read CLIDR
208 ands R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC)
209 mov R3, R3, LSR #23 ; Cache level value (naturally aligned)
210 beq Finished
211 mov R10, #0
212
213 Loop1
214 add R2, R10, R10, LSR #1 ; Work out 3xcachelevel
215 mov R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level
216 and R12, R12, #7 ; get those 3 bits alone
217 cmp R12, #2
218 blt Skip ; no cache or only instruction cache at this level
219 mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
220 isb ; isb to sync the change to the CacheSizeID reg
221 mrc p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)
222 and R2, R12, #&7 ; extract the line length field
223 add R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)
224 ldr R4, =0x3FF
225 ands R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)
226 clz R5, R4 ; R5 is the bit position of the way size increment
227 ldr R7, =0x00007FFF
228 ands R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)
229
230 Loop2
231 mov R9, R4 ; R9 working copy of the max way size (right aligned)
232
233 Loop3
234 orr R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11
235 orr R0, R0, R7, LSL R2 ; factor in the index number
236
237 blx R1
238
239 subs R9, R9, #1 ; decrement the way number
240 bge Loop3
241 subs R7, R7, #1 ; decrement the index
242 bge Loop2
243 Skip
244 add R10, R10, #2 ; increment the cache number
245 cmp R3, R10
246 bgt Loop1
247
248 Finished
249 dsb
250 ldmfd SP!, {r4-r12, lr}
251 bx LR
252
253 ArmDataMemoryBarrier
254 dmb
255 bx LR
256
257 ArmDataSynchronizationBarrier
258 ArmDrainWriteBuffer
259 dsb
260 bx LR
261
262 ArmInstructionSynchronizationBarrier
263 isb
264 bx LR
265
266 ArmReadVBar
267 // Set the Address of the Vector Table in the VBAR register
268 mrc p15, 0, r0, c12, c0, 0
269 bx lr
270
271 ArmWriteVBar
272 // Set the Address of the Vector Table in the VBAR register
273 mcr p15, 0, r0, c12, c0, 0
274 // Ensure the SCTLR.V bit is clear
275 mrc p15, 0, r0, c1, c0, 0 ; Read SCTLR into R0 (Read control register configuration data)
276 bic r0, r0, #0x00002000 ; clear V bit
277 mcr p15, 0, r0, c1, c0, 0 ; Write R0 into SCTLR (Write control register configuration data)
278 isb
279 bx lr
280
281 ArmEnableVFP
282 // Read CPACR (Coprocessor Access Control Register)
283 mrc p15, 0, r0, c1, c0, 2
284 // Enable VPF access (Full Access to CP10, CP11) (V* instructions)
285 orr r0, r0, #0x00f00000
286 // Write back CPACR (Coprocessor Access Control Register)
287 mcr p15, 0, r0, c1, c0, 2
288 isb
289 // Set EN bit in FPEXC. The Advanced SIMD and VFP extensions are enabled and operate normally.
290 mov r0, #0x40000000
291 mcr p10,#0x7,r0,c8,c0,#0
292 bx lr
293
294 ArmCallWFI
295 wfi
296 bx lr
297
298 //Note: Return 0 in Uniprocessor implementation
299 ArmReadCbar
300 mrc p15, 4, r0, c15, c0, 0 //Read Configuration Base Address Register
301 bx lr
302
303 ArmReadMpidr
304 mrc p15, 0, r0, c0, c0, 5 ; read MPIDR
305 bx lr
306
307 ArmReadTpidrurw
308 mrc p15, 0, r0, c13, c0, 2 ; read TPIDRURW
309 bx lr
310
311 ArmWriteTpidrurw
312 mcr p15, 0, r0, c13, c0, 2 ; write TPIDRURW
313 bx lr
314
315 ArmIsArchTimerImplemented
316 mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1
317 and r0, r0, #0x000F0000
318 bx lr
319
320 ArmReadIdPfr1
321 mrc p15, 0, r0, c0, c1, 1 ; Read ID_PFR1 Register
322 bx lr
323
324 ArmReadIdMmfr0
325 mrc p15, 0, r0, c0, c1, 4 ; Read ID_MMFR0 Register
326 bx lr
327
328 END