1 //------------------------------------------------------------------------------
3 // Copyright (c) 2008-2009 Apple Inc. All rights reserved.
5 // All rights reserved. This program and the accompanying materials
6 // are licensed and made available under the terms and conditions of the BSD License
7 // which accompanies this distribution. The full text of the license may be found at
8 // http://opensource.org/licenses/bsd-license.php
10 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 //------------------------------------------------------------------------------
15 EXPORT ArmInvalidateInstructionCache
16 EXPORT ArmInvalidateDataCacheEntryByMVA
17 EXPORT ArmCleanDataCacheEntryByMVA
18 EXPORT ArmCleanInvalidateDataCacheEntryByMVA
19 EXPORT ArmInvalidateDataCacheEntryBySetWay
20 EXPORT ArmCleanDataCacheEntryBySetWay
21 EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
22 EXPORT ArmDrainWriteBuffer
26 EXPORT ArmEnableDataCache
27 EXPORT ArmDisableDataCache
28 EXPORT ArmEnableInstructionCache
29 EXPORT ArmDisableInstructionCache
30 EXPORT ArmEnableBranchPrediction
31 EXPORT ArmDisableBranchPrediction
32 EXPORT ArmV7AllDataCachesOperation
33 EXPORT ArmDataMemoryBarrier
34 EXPORT ArmDataSyncronizationBarrier
35 EXPORT ArmInstructionSynchronizationBarrier
38 DC_ON EQU ( 0x1:SHL:2 )
39 IC_ON EQU ( 0x1:SHL:12 )
42 AREA ArmCacheLib, CODE, READONLY
46 ArmInvalidateDataCacheEntryByMVA
47 MCR p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
53 ArmCleanDataCacheEntryByMVA
54 MCR p15, 0, r0, c7, c10, 1 ; clean single data cache line
60 ArmCleanInvalidateDataCacheEntryByMVA
61 MCR p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
67 ArmInvalidateDataCacheEntryBySetWay
68 mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
74 ArmCleanInvalidateDataCacheEntryBySetWay
75 mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
81 ArmCleanDataCacheEntryBySetWay
82 mcr p15, 0, r0, c7, c10, 2 ; Clean this line
89 mcr p15, 0, r0, c7, c10, 4 ; Drain write buffer for sync
95 ArmInvalidateInstructionCache
97 MCR p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
99 MCR p15,0,R0,c7,c5,4 ;Instruction synchronization barrier
120 mcr p15,0,R0,c13,c0,0 ;FCSE PID register must be cleared before disabling MMU
123 mcr p15,0,R0,c1,c0,0 ;Disable MMU
130 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
131 ORR R0,R0,R1 ;Set C bit
132 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
139 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
140 BIC R0,R0,R1 ;Clear C bit
141 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
145 ArmEnableInstructionCache
147 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
148 ORR R0,R0,R1 ;Set I bit
149 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
153 ArmDisableInstructionCache
155 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
156 BIC R0,R0,R1 ;Clear I bit.
157 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
161 ArmEnableBranchPrediction
162 mrc p15, 0, r0, c1, c0, 0
163 orr r0, r0, #0x00000800
164 mcr p15, 0, r0, c1, c0, 0
168 ArmDisableBranchPrediction
169 mrc p15, 0, r0, c1, c0, 0
170 bic r0, r0, #0x00000800
171 mcr p15, 0, r0, c1, c0, 0
176 ArmV7AllDataCachesOperation
177 STMFD SP!,{r4-r12, LR}
178 MOV R1, R0 ; Save Function call in R1
179 MRC p15, 1, R6, c0, c0, 1 ; Read CLIDR
180 ANDS R3, R6, #&7000000 ; Mask out all but Level of Coherency (LoC)
181 MOV R3, R3, LSR #23 ; Cache level value (naturally aligned)
186 ADD R2, R10, R10, LSR #1 ; Work out 3xcachelevel
187 MOV R12, R6, LSR R2 ; bottom 3 bits are the Cache type for this level
188 AND R12, R12, #7 ; get those 3 bits alone
190 BLT Skip ; no cache or only instruction cache at this level
191 MCR p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
192 ISB ; ISB to sync the change to the CacheSizeID reg
193 MRC p15, 1, R12, c0, c0, 0 ; reads current Cache Size ID register (CCSIDR)
194 AND R2, R12, #&7 ; extract the line length field
195 ADD R2, R2, #4 ; add 4 for the line length offset (log2 16 bytes)
197 ANDS R4, R4, R12, LSR #3 ; R4 is the max number on the way size (right aligned)
198 CLZ R5, R4 ; R5 is the bit position of the way size increment
200 ANDS R7, R7, R12, LSR #13 ; R7 is the max number of the index size (right aligned)
203 MOV R9, R4 ; R9 working copy of the max way size (right aligned)
206 ORR R0, R10, R9, LSL R5 ; factor in the way number and cache number into R11
207 ORR R0, R0, R7, LSL R2 ; factor in the index number
211 SUBS R9, R9, #1 ; decrement the way number
213 SUBS R7, R7, #1 ; decrement the index
216 ADD R10, R10, #2 ; increment the cache number
221 LDMFD SP!, {r4-r12, lr}
229 ArmDataSyncronizationBarrier
233 ArmInstructionSynchronizationBarrier