1 //------------------------------------------------------------------------------
3 // Copyright (c) 2008-2009 Apple Inc. All rights reserved.
5 // All rights reserved. This program and the accompanying materials
6 // are licensed and made available under the terms and conditions of the BSD License
7 // which accompanies this distribution. The full text of the license may be found at
8 // http://opensource.org/licenses/bsd-license.php
10 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 //------------------------------------------------------------------------------
15 EXPORT ArmInvalidateInstructionCache
16 EXPORT ArmInvalidateDataCacheEntryByMVA
17 EXPORT ArmCleanDataCacheEntryByMVA
18 EXPORT ArmCleanInvalidateDataCacheEntryByMVA
19 EXPORT ArmInvalidateDataCacheEntryBySetWay
20 EXPORT ArmCleanDataCacheEntryBySetWay
21 EXPORT ArmCleanInvalidateDataCacheEntryBySetWay
22 EXPORT ArmDrainWriteBuffer
26 EXPORT ArmEnableDataCache
27 EXPORT ArmDisableDataCache
28 EXPORT ArmEnableInstructionCache
29 EXPORT ArmDisableInstructionCache
30 EXPORT ArmEnableBranchPrediction
31 EXPORT ArmDisableBranchPrediction
33 DC_ON EQU ( 0x1:SHL:2 )
34 IC_ON EQU ( 0x1:SHL:12 )
35 XP_ON EQU ( 0x1:SHL:23 )
38 AREA ArmCacheLib, CODE, READONLY
42 ArmInvalidateDataCacheEntryByMVA
43 MCR p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
47 ArmCleanDataCacheEntryByMVA
48 MCR p15, 0, r0, c7, c10, 1 ; clean single data cache line
52 ArmCleanInvalidateDataCacheEntryByMVA
53 MCR p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
57 ArmInvalidateDataCacheEntryBySetWay
58 mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
62 ArmCleanInvalidateDataCacheEntryBySetWay
63 mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
67 ArmCleanDataCacheEntryBySetWay
68 mcr p15, 0, r0, c7, c10, 2 ; Clean this line
73 mcr p15, 0, r0, c7, c10, 4 ; Drain write buffer for sync
77 ArmInvalidateInstructionCache
79 MCR p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
81 MCR p15,0,R0,c7,c5,4 ;Instruction synchronization barrier
97 mcr p15,0,R0,c13,c0,0 ;FCSE PID register must be cleared before disabling MMU
100 mcr p15,0,R0,c1,c0,0 ;Disable MMU
102 mcr p15,0,R0,c7,c10,4 ;Data synchronization barrier
104 mcr p15,0,R0,c7,c5,4 ;Instruction synchronization barrier
109 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
110 ORR R0,R0,R1 ;Set C bit
111 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
116 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
117 BIC R0,R0,R1 ;Clear C bit
118 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
121 ArmEnableInstructionCache
123 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
124 ORR R0,R0,R1 ;Set I bit
125 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
128 ArmDisableInstructionCache
130 MRC p15,0,R0,c1,c0,0 ;Read control register configuration data
131 BIC R0,R0,R1 ;Clear I bit.
132 MCR p15,0,r0,c1,c0,0 ;Write control register configuration data
135 ArmEnableBranchPrediction
136 mrc p15, 0, r0, c1, c0, 0
137 orr r0, r0, #0x00000800
138 mcr p15, 0, r0, c1, c0, 0
141 ArmDisableBranchPrediction
142 mrc p15, 0, r0, c1, c0, 0
143 bic r0, r0, #0x00000800
144 mcr p15, 0, r0, c1, c0, 0