ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm

   1 //------------------------------------------------------------------------------
   2 //
   3 // Copyright (c) 2008-2009 Apple Inc. All rights reserved.
   4 //
   5 // All rights reserved. This program and the accompanying materials
   6 // are licensed and made available under the terms and conditions of the BSD License
   7 // which accompanies this distribution.  The full text of the license may be found at
   8 // http://opensource.org/licenses/bsd-license.php
   9 //
  10 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 //
  13 //------------------------------------------------------------------------------
  14
  15     EXPORT  ArmInvalidateInstructionCache
  16     EXPORT  ArmInvalidateDataCacheEntryByMVA
  17     EXPORT  ArmCleanDataCacheEntryByMVA
  18     EXPORT  ArmCleanInvalidateDataCacheEntryByMVA
  19     EXPORT  ArmInvalidateDataCacheEntryBySetWay
  20     EXPORT  ArmCleanDataCacheEntryBySetWay
  21     EXPORT  ArmCleanInvalidateDataCacheEntryBySetWay
  22     EXPORT  ArmDrainWriteBuffer
  23     EXPORT  ArmEnableMmu
  24     EXPORT  ArmDisableMmu
  25     EXPORT  ArmMmuEnabled
  26     EXPORT  ArmEnableDataCache
  27     EXPORT  ArmDisableDataCache
  28     EXPORT  ArmEnableInstructionCache
  29     EXPORT  ArmDisableInstructionCache
  30     EXPORT  ArmEnableBranchPrediction
  31     EXPORT  ArmDisableBranchPrediction
  32
  33 DC_ON       EQU     ( 0x1:SHL:2 )
  34 IC_ON       EQU     ( 0x1:SHL:12 )
  35
  36
  37     AREA    ArmCacheLib, CODE, READONLY
  38     PRESERVE8
  39
  40
  41 ArmInvalidateDataCacheEntryByMVA
  42   MCR     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line
  43   DSB
  44   ISB
  45   BX      lr
  46
  47
  48 ArmCleanDataCacheEntryByMVA
  49   MCR     p15, 0, r0, c7, c10, 1  ; clean single data cache line
  50   DSB
  51   ISB
  52   BX      lr
  53
  54
  55 ArmCleanInvalidateDataCacheEntryByMVA
  56   MCR     p15, 0, r0, c7, c14, 1  ; clean and invalidate single data cache line
  57   DSB
  58   ISB
  59   BX      lr
  60
  61
  62 ArmInvalidateDataCacheEntryBySetWay
  63   mcr     p15, 0, r0, c7, c6, 2        ; Invalidate this line
  64   DSB
  65   ISB
  66   bx      lr
  67
  68
  69 ArmCleanInvalidateDataCacheEntryBySetWay
  70   mcr     p15, 0, r0, c7, c14, 2       ; Clean and Invalidate this line
  71   DSB
  72   ISB
  73   bx      lr
  74
  75
  76 ArmCleanDataCacheEntryBySetWay
  77   mcr     p15, 0, r0, c7, c10, 2       ; Clean this line
  78   DSB
  79   ISB
  80   bx      lr
  81
  82
  83 ArmDrainWriteBuffer
  84   mcr     p15, 0, r0, c7, c10, 4       ; Drain write buffer for sync
  85   DSB
  86   ISB
  87   bx      lr
  88
  89
  90 ArmInvalidateInstructionCache
  91   MOV     R0,#0
  92   MCR     p15,0,R0,c7,c5,0      ;Invalidate entire instruction cache
  93   MOV     R0,#0
  94   MCR     p15,0,R0,c7,c5,4      ;Instruction synchronization barrier
  95   DSB
  96   ISB
  97   BX      LR
  98
  99 ArmEnableMmu
 100   mrc     p15,0,R0,c1,c0,0
 101   orr     R0,R0,#1
 102   mcr     p15,0,R0,c1,c0,0
 103   DSB
 104   ISB
 105   bx      LR
 106
 107 ArmMmuEnabled
 108   mrc     p15,0,R0,c1,c0,0
 109   and     R0,R0,#1
 110   ISB
 111   bx      LR
 112
 113 ArmDisableMmu
 114   mov     R0,#0
 115   mcr     p15,0,R0,c13,c0,0     ;FCSE PID register must be cleared before disabling MMU
 116   mrc     p15,0,R0,c1,c0,0
 117   bic     R0,R0,#1
 118   mcr     p15,0,R0,c1,c0,0      ;Disable MMU
 119   DSB
 120   ISB
 121   bx      LR
 122
 123 ArmEnableDataCache
 124   LDR     R1,=DC_ON
 125   MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data
 126   ORR     R0,R0,R1              ;Set C bit
 127   MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data
 128   DSB
 129   ISB
 130   BX      LR
 131
 132 ArmDisableDataCache
 133   LDR     R1,=DC_ON
 134   MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data
 135   BIC     R0,R0,R1              ;Clear C bit
 136   MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data
 137   ISB
 138   BX      LR
 139
 140 ArmEnableInstructionCache
 141   LDR     R1,=IC_ON
 142   MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data
 143   ORR     R0,R0,R1              ;Set I bit
 144   MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data
 145   ISB
 146   BX      LR
 147
 148 ArmDisableInstructionCache
 149   LDR     R1,=IC_ON
 150   MRC     p15,0,R0,c1,c0,0     ;Read control register configuration data
 151   BIC     R0,R0,R1             ;Clear I bit.
 152   MCR     p15,0,r0,c1,c0,0     ;Write control register configuration data
 153   ISB
 154   BX      LR
 155
 156 ArmEnableBranchPrediction
 157   mrc     p15, 0, r0, c1, c0, 0
 158   orr     r0, r0, #0x00000800
 159   mcr     p15, 0, r0, c1, c0, 0
 160   ISB
 161   bx      LR
 162
 163 ArmDisableBranchPrediction
 164   mrc     p15, 0, r0, c1, c0, 0
 165   bic     r0, r0, #0x00000800
 166   mcr     p15, 0, r0, c1, c0, 0
 167   ISB
 168   bx      LR
 169
 170
 171 ArmV7AllDataCachesOperation
 172   STMFD SP!,{r4-r12, LR}
 173   MOV   R1, R0                ; Save Function call in R1
 174   MRC   p15, 1, R6, c0, c0, 1 ; Read CLIDR
 175   ANDS  R3, R6, #&7000000     ; Mask out all but Level of Coherency (LoC)
 176   MOV   R3, R3, LSR #23       ; Cache level value (naturally aligned)
 177   BEQ   Finished
 178   MOV   R10, #0
 179
 180 Loop1
 181   ADD   R2, R10, R10, LSR #1  ; Work out 3xcachelevel
 182   MOV   R12, R6, LSR R2       ; bottom 3 bits are the Cache type for this level
 183   AND   R12, R12, #7          ; get those 3 bits alone
 184   CMP   R12, #2
 185   BLT   Skip                    ; no cache or only instruction cache at this level
 186   MCR   p15, 2, R10, c0, c0, 0  ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
 187   ISB                           ; ISB to sync the change to the CacheSizeID reg
 188   MRC   p15, 1, R12, c0, c0, 0  ; reads current Cache Size ID register (CCSIDR)
 189   AND   R2, R12, #&7            ; extract the line length field
 190   ADD   R2, R2, #4              ; add 4 for the line length offset (log2 16 bytes)
 191   LDR   R4, =0x3FF
 192   ANDS  R4, R4, R12, LSR #3     ; R4 is the max number on the way size (right aligned)
 193   CLZ   R5, R4                  ; R5 is the bit position of the way size increment
 194   LDR   R7, =0x00007FFF
 195   ANDS  R7, R7, R12, LSR #13    ; R7 is the max number of the index size (right aligned)
 196
 197 Loop2
 198   MOV   R9, R4                  ; R9 working copy of the max way size (right aligned)
 199
 200 Loop3
 201   ORR   R0, R10, R9, LSL R5     ; factor in the way number and cache number into R11
 202   ORR   R0, R0, R7, LSL R2      ; factor in the index number
 203
 204   BLX   R1
 205
 206   SUBS  R9, R9, #1              ; decrement the way number
 207   BGE   Loop3
 208   SUBS  R7, R7, #1              ; decrement the index
 209   BGE   Loop2
 210 Skip
 211   ADD   R10, R10, #2            ; increment the cache number
 212   CMP   R3, R10
 213   BGT   Loop1
 214
 215 Finished
 216   LDMFD SP!, {r4-r12, lr}
 217   BX    LR
 218
 219     END