ArmPkg/Library/ArmLib/Common/Arm/ArmLibSupport.asm

   1 //------------------------------------------------------------------------------
   2 //
   3 // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4 // Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
   5 //
   6 // This program and the accompanying materials
   7 // are licensed and made available under the terms and conditions of the BSD License
   8 // which accompanies this distribution.  The full text of the license may be found at
   9 // http://opensource.org/licenses/bsd-license.php
  10 //
  11 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 //
  14 //------------------------------------------------------------------------------
  15
  16 #include <AsmMacroIoLib.h>
  17
  18     INCLUDE AsmMacroIoLib.inc
  19
  20 #ifdef ARM_CPU_ARMv6
  21 // No memory barriers for ARMv6
  22 #define isb
  23 #define dsb
  24 #endif
  25
  26     EXPORT ArmReadMidr
  27     EXPORT ArmCacheInfo
  28     EXPORT ArmGetInterruptState
  29     EXPORT ArmGetFiqState
  30     EXPORT ArmGetTTBR0BaseAddress
  31     EXPORT ArmSetTTBR0
  32     EXPORT ArmSetDomainAccessControl
  33     EXPORT CPSRMaskInsert
  34     EXPORT CPSRRead
  35     EXPORT ArmReadCpacr
  36     EXPORT ArmWriteCpacr
  37     EXPORT ArmWriteAuxCr
  38     EXPORT ArmReadAuxCr
  39     EXPORT ArmInvalidateTlb
  40     EXPORT ArmUpdateTranslationTableEntry
  41     EXPORT ArmReadScr
  42     EXPORT ArmWriteScr
  43     EXPORT ArmReadMVBar
  44     EXPORT ArmWriteMVBar
  45     EXPORT ArmReadHVBar
  46     EXPORT ArmWriteHVBar
  47     EXPORT ArmCallWFE
  48     EXPORT ArmCallSEV
  49     EXPORT ArmReadSctlr
  50     EXPORT ArmReadCpuActlr
  51     EXPORT ArmWriteCpuActlr
  52
  53     AREA ArmLibSupport, CODE, READONLY
  54
  55 ArmReadMidr
  56   mrc     p15,0,R0,c0,c0,0
  57   bx      LR
  58
  59 ArmCacheInfo
  60   mrc     p15,0,R0,c0,c0,1
  61   bx      LR
  62
  63 ArmGetInterruptState
  64   mrs     R0,CPSR
  65   tst     R0,#0x80      // Check if IRQ is enabled.
  66   moveq   R0,#1
  67   movne   R0,#0
  68   bx      LR
  69
  70 ArmGetFiqState
  71   mrs     R0,CPSR
  72   tst     R0,#0x40      // Check if FIQ is enabled.
  73   moveq   R0,#1
  74   movne   R0,#0
  75   bx      LR
  76
  77 ArmSetDomainAccessControl
  78   mcr     p15,0,r0,c3,c0,0
  79   bx      lr
  80
  81 CPSRMaskInsert    // on entry, r0 is the mask and r1 is the field to insert
  82   stmfd   sp!, {r4-r12, lr} // save all the banked registers
  83   mov     r3, sp            // copy the stack pointer into a non-banked register
  84   mrs     r2, cpsr          // read the cpsr
  85   bic     r2, r2, r0        // clear mask in the cpsr
  86   and     r1, r1, r0        // clear bits outside the mask in the input
  87   orr     r2, r2, r1        // set field
  88   msr     cpsr_cxsf, r2     // write back cpsr (may have caused a mode switch)
  89   isb
  90   mov     sp, r3            // restore stack pointer
  91   ldmfd   sp!, {r4-r12, lr} // restore registers
  92   bx      lr                // return (hopefully thumb-safe!)             // return (hopefully thumb-safe!)
  93
  94 CPSRRead
  95   mrs     r0, cpsr
  96   bx      lr
  97
  98 ArmReadCpacr
  99   mrc     p15, 0, r0, c1, c0, 2
 100   bx      lr
 101
 102 ArmWriteCpacr
 103   mcr     p15, 0, r0, c1, c0, 2
 104   isb
 105   bx      lr
 106
 107 ArmWriteAuxCr
 108   mcr     p15, 0, r0, c1, c0, 1
 109   bx      lr
 110
 111 ArmReadAuxCr
 112   mrc     p15, 0, r0, c1, c0, 1
 113   bx      lr
 114
 115 ArmSetTTBR0
 116   mcr     p15,0,r0,c2,c0,0
 117   isb
 118   bx      lr
 119
 120 ArmGetTTBR0BaseAddress
 121   mrc     p15,0,r0,c2,c0,0
 122   LoadConstantToReg(0xFFFFC000, r1)
 123   and     r0, r0, r1
 124   isb
 125   bx      lr
 126
 127 //
 128 //VOID
 129 //ArmUpdateTranslationTableEntry (
 130 //  IN VOID  *TranslationTableEntry  // R0
 131 //  IN VOID  *MVA                    // R1
 132 //  );
 133 ArmUpdateTranslationTableEntry
 134   mcr     p15,0,R0,c7,c14,1     // DCCIMVAC Clean data cache by MVA
 135   dsb
 136   mcr     p15,0,R1,c8,c7,1      // TLBIMVA TLB Invalidate MVA
 137   mcr     p15,0,R9,c7,c5,6      // BPIALL Invalidate Branch predictor array. R9 == NoOp
 138   dsb
 139   isb
 140   bx      lr
 141
 142 ArmInvalidateTlb
 143   mov     r0,#0
 144   mcr     p15,0,r0,c8,c7,0
 145   mcr     p15,0,R9,c7,c5,6      // BPIALL Invalidate Branch predictor array. R9 == NoOp
 146   dsb
 147   isb
 148   bx      lr
 149
 150 ArmReadScr
 151   mrc     p15, 0, r0, c1, c1, 0
 152   bx      lr
 153
 154 ArmWriteScr
 155   mcr     p15, 0, r0, c1, c1, 0
 156   bx      lr
 157
 158 ArmReadHVBar
 159   mrc     p15, 4, r0, c12, c0, 0
 160   bx      lr
 161
 162 ArmWriteHVBar
 163   mcr     p15, 4, r0, c12, c0, 0
 164   bx      lr
 165
 166 ArmReadMVBar
 167   mrc     p15, 0, r0, c12, c0, 1
 168   bx      lr
 169
 170 ArmWriteMVBar
 171   mcr     p15, 0, r0, c12, c0, 1
 172   bx      lr
 173
 174 ArmCallWFE
 175   wfe
 176   bx      lr
 177
 178 ArmCallSEV
 179   sev
 180   bx      lr
 181
 182 ArmReadSctlr
 183   mrc     p15, 0, r0, c1, c0, 0      // Read SCTLR into R0 (Read control register configuration data)
 184   bx      lr
 185
 186
 187 ArmReadCpuActlr
 188   mrc     p15, 0, r0, c1, c0, 1
 189   bx      lr
 190
 191 ArmWriteCpuActlr
 192   mcr     p15, 0, r0, c1, c0, 1
 193   dsb
 194   isb
 195   bx      lr
 196
 197   END