ArmPkg/Library/ArmLib/Common/ArmLibSupport.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008-2009 Apple Inc. All rights reserved.
   4 #
   5 # All rights reserved. This program and the accompanying materials
   6 # are licensed and made available under the terms and conditions of the BSD License
   7 # which accompanies this distribution.  The full text of the license may be found at
   8 # http://opensource.org/licenses/bsd-license.php
   9 #
  10 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 #
  13 #------------------------------------------------------------------------------
  14
  15 .text
  16 .align 2
  17 .globl ASM_PFX(Cp15IdCode)
  18 .globl ASM_PFX(Cp15CacheInfo)
  19 .globl ASM_PFX(ArmEnableInterrupts)
  20 .globl ASM_PFX(ArmDisableInterrupts)
  21 .globl ASM_PFX(ArmGetInterruptState)
  22 .globl ASM_PFX(ArmInvalidateTlb)
  23 .globl ASM_PFX(ArmSetTranslationTableBaseAddress)
  24 .globl ASM_PFX(ArmGetTranslationTableBaseAddress)
  25 .globl ASM_PFX(ArmSetDomainAccessControl)
  26 .globl ASM_PFX(CPSRMaskInsert)
  27 .globl ASM_PFX(CPSRRead)
  28
  29 #------------------------------------------------------------------------------
  30
  31 ASM_PFX(Cp15IdCode):
  32   mrc     p15,0,R0,c0,c0,0
  33   bx      LR
  34
  35 ASM_PFX(Cp15CacheInfo):
  36   mrc     p15,0,R0,c0,c0,1
  37   bx      LR
  38
  39 ASM_PFX(ArmEnableInterrupts):
  40         mrs     R0,CPSR
  41         bic     R0,R0,#0x80             @Enable IRQ interrupts
  42         msr     CPSR_c,R0
  43         bx      LR
  44
  45 ASM_PFX(ArmDisableInterrupts):
  46         mrs     R0,CPSR
  47         orr     R1,R0,#0x80             @Disable IRQ interrupts
  48         msr     CPSR_c,R1
  49   tst     R0,#0x80
  50   moveq   R0,#1
  51   movne   R0,#0
  52         bx      LR
  53
  54 ASM_PFX(ArmGetInterruptState):
  55         mrs     R0,CPSR
  56         tst     R0,#0x80            @Check if IRQ is enabled.
  57         moveq   R0,#1
  58         movne   R0,#0
  59         bx      LR
  60
  61 ASM_PFX(ArmInvalidateTlb):
  62   mov     r0,#0
  63   mcr     p15,0,r0,c8,c7,0
  64   bx      lr
  65
  66 ASM_PFX(ArmSetTranslationTableBaseAddress):
  67   mcr     p15,0,r0,c2,c0,0
  68   bx      lr
  69
  70 ASM_PFX(ArmGetTranslationTableBaseAddress):
  71   mrc     p15,0,r0,c2,c0,0
  72   bx      lr
  73
  74
  75 ASM_PFX(ArmSetDomainAccessControl):
  76   mcr     p15,0,r0,c3,c0,0
  77   bx      lr
  78
  79 ASM_PFX(CPSRMaskInsert):    @ on entry, r0 is the mask and r1 is the field to insert
  80   stmfd   sp!, {r4-r12, lr} @ save all the banked registers
  81   mov     r3, sp            @ copy the stack pointer into a non-banked register
  82   mrs     r2, cpsr          @ read the cpsr
  83   bic     r2, r2, r0        @ clear mask in the cpsr
  84   and     r1, r1, r0        @ clear bits outside the mask in the input
  85   orr     r2, r2, r1        @ set field
  86   msr     cpsr_cxsf, r2     @ write back cpsr (may have caused a mode switch)
  87   mov     sp, r3            @ restore stack pointer
  88   ldmfd   sp!, {r4-r12, lr} @ restore registers
  89   bx      lr                @ return (hopefully thumb-safe!)
  90
  91 ASM_PFX(CPSRRead):
  92   mrs     r0, cpsr
  93   bx      lr
  94
  95 ASM_FUNCTION_REMOVE_IF_UNREFERENCED