ArmPkg/Library/ArmLib/Common/ArmLibSupport.S

   1 #------------------------------------------------------------------------------
   2 #
   3 # Copyright (c) 2008-2009 Apple Inc. All rights reserved.
   4 #
   5 # All rights reserved. This program and the accompanying materials
   6 # are licensed and made available under the terms and conditions of the BSD License
   7 # which accompanies this distribution.  The full text of the license may be found at
   8 # http://opensource.org/licenses/bsd-license.php
   9 #
  10 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 #
  13 #------------------------------------------------------------------------------
  14
  15 .text
  16 .align 2
  17 .globl ASM_PFX(Cp15IdCode)
  18 .globl ASM_PFX(Cp15CacheInfo)
  19 .globl ASM_PFX(ArmEnableInterrupts)
  20 .globl ASM_PFX(ArmDisableInterrupts)
  21 .globl ASM_PFX(ArmGetInterruptState)
  22 .globl ASM_PFX(ArmInvalidateTlb)
  23 .globl ASM_PFX(ArmSetTranslationTableBaseAddress)
  24 .globl ASM_PFX(ArmSetDomainAccessControl)
  25 .globl ASM_PFX(CPSRMaskInsert)
  26 .globl ASM_PFX(CPSRRead)
  27
  28 #------------------------------------------------------------------------------
  29
  30 ASM_PFX(Cp15IdCode):
  31   mrc     p15,0,R0,c0,c0,0
  32   bx      LR
  33
  34 ASM_PFX(Cp15CacheInfo):
  35   mrc     p15,0,R0,c0,c0,1
  36   bx      LR
  37
  38 ASM_PFX(ArmEnableInterrupts):
  39         mrs     R0,CPSR
  40         bic     R0,R0,#0x80             @Enable IRQ interrupts
  41         msr     CPSR_c,R0
  42         bx      LR
  43
  44 ASM_PFX(ArmDisableInterrupts):
  45         mrs     R0,CPSR
  46         orr     R1,R0,#0x80             @Disable IRQ interrupts
  47         msr     CPSR_c,R1
  48   tst     R0,#0x80
  49   moveq   R0,#1
  50   movne   R0,#0
  51         bx      LR
  52
  53 ASM_PFX(ArmGetInterruptState):
  54         mrs     R0,CPSR
  55         tst     R0,#0x80            @Check if IRQ is enabled.
  56         moveq   R0,#1
  57         movne   R0,#0
  58         bx      LR
  59
  60 ASM_PFX(ArmInvalidateTlb):
  61   mov     r0,#0
  62   mcr     p15,0,r0,c8,c7,0
  63   bx      lr
  64
  65 ASM_PFX(ArmSetTranslationTableBaseAddress):
  66   mcr     p15,0,r0,c2,c0,0
  67   bx      lr
  68
  69 ASM_PFX(ArmSetDomainAccessControl):
  70   mcr     p15,0,r0,c3,c0,0
  71   bx      lr
  72
  73 ASM_PFX(CPSRMaskInsert):    @ on entry, r0 is the mask and r1 is the field to insert
  74   stmfd   sp!, {r4-r12, lr} @ save all the banked registers
  75   mov     r3, sp            @ copy the stack pointer into a non-banked register
  76   mrs     r2, cpsr          @ read the cpsr
  77   bic     r2, r2, r0        @ clear mask in the cpsr
  78   and     r1, r1, r0        @ clear bits outside the mask in the input
  79   orr     r2, r2, r1        @ set field
  80   msr     cpsr_cxsf, r2     @ write back cpsr (may have caused a mode switch)
  81   mov     sp, r3            @ restore stack pointer
  82   ldmfd   sp!, {r4-r12, lr} @ restore registers
  83   bx      lr                @ return (hopefully thumb-safe!)
  84
  85 ASM_PFX(CPSRRead):
  86   mrs     r0, cpsr
  87   bx      lr
  88
  89 ASM_FUNCTION_REMOVE_IF_UNREFERENCED