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1 #------------------------------------------------------------------------------
2 #
3 # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
4 #
5 # This program and the accompanying materials
6 # are licensed and made available under the terms and conditions of the BSD License
7 # which accompanies this distribution. The full text of the license may be found at
8 # http://opensource.org/licenses/bsd-license.php
9 #
10 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12 #
13 #------------------------------------------------------------------------------
14
15 .text
16 .align 2
17 .globl ASM_PFX(Cp15IdCode)
18 .globl ASM_PFX(Cp15CacheInfo)
19 .globl ASM_PFX(ArmEnableInterrupts)
20 .globl ASM_PFX(ArmDisableInterrupts)
21 .globl ASM_PFX(ArmGetInterruptState)
22 .globl ASM_PFX(ArmEnableFiq)
23 .globl ASM_PFX(ArmDisableFiq)
24 .globl ASM_PFX(ArmGetFiqState)
25 .globl ASM_PFX(ArmInvalidateTlb)
26 .globl ASM_PFX(ArmSetTranslationTableBaseAddress)
27 .globl ASM_PFX(ArmGetTranslationTableBaseAddress)
28 .globl ASM_PFX(ArmSetDomainAccessControl)
29 .globl ASM_PFX(CPSRMaskInsert)
30 .globl ASM_PFX(CPSRRead)
31
32 #------------------------------------------------------------------------------
33
34 ASM_PFX(Cp15IdCode):
35 mrc p15,0,R0,c0,c0,0
36 bx LR
37
38 ASM_PFX(Cp15CacheInfo):
39 mrc p15,0,R0,c0,c0,1
40 bx LR
41
42 ASM_PFX(ArmEnableInterrupts):
43 mrs R0,CPSR
44 bic R0,R0,#0x80 @Enable IRQ interrupts
45 msr CPSR_c,R0
46 bx LR
47
48 ASM_PFX(ArmDisableInterrupts):
49 mrs R0,CPSR
50 orr R1,R0,#0x80 @Disable IRQ interrupts
51 msr CPSR_c,R1
52 tst R0,#0x80
53 moveq R0,#1
54 movne R0,#0
55 bx LR
56
57 ASM_PFX(ArmGetInterruptState):
58 mrs R0,CPSR
59 tst R0,#0x80 @Check if IRQ is enabled.
60 moveq R0,#1
61 movne R0,#0
62 bx LR
63
64 ASM_PFX(ArmEnableFiq):
65 mrs R0,CPSR
66 bic R0,R0,#0x40 @Enable FIQ interrupts
67 msr CPSR_c,R0
68 bx LR
69
70 ASM_PFX(ArmDisableFiq):
71 mrs R0,CPSR
72 orr R1,R0,#0x40 @Disable FIQ interrupts
73 msr CPSR_c,R1
74 tst R0,#0x80
75 moveq R0,#1
76 movne R0,#0
77 bx LR
78
79 ASM_PFX(ArmGetFiqState):
80 mrs R0,CPSR
81 tst R0,#0x80 @Check if FIQ is enabled.
82 moveq R0,#1
83 movne R0,#0
84 bx LR
85
86 ASM_PFX(ArmInvalidateTlb):
87 mov r0,#0
88 mcr p15,0,r0,c8,c7,0
89 bx lr
90
91 ASM_PFX(ArmSetTranslationTableBaseAddress):
92 mcr p15,0,r0,c2,c0,0
93 bx lr
94
95 ASM_PFX(ArmGetTranslationTableBaseAddress):
96 mrc p15,0,r0,c2,c0,0
97 bx lr
98
99
100 ASM_PFX(ArmSetDomainAccessControl):
101 mcr p15,0,r0,c3,c0,0
102 bx lr
103
104 ASM_PFX(CPSRMaskInsert): @ on entry, r0 is the mask and r1 is the field to insert
105 stmfd sp!, {r4-r12, lr} @ save all the banked registers
106 mov r3, sp @ copy the stack pointer into a non-banked register
107 mrs r2, cpsr @ read the cpsr
108 bic r2, r2, r0 @ clear mask in the cpsr
109 and r1, r1, r0 @ clear bits outside the mask in the input
110 orr r2, r2, r1 @ set field
111 msr cpsr_cxsf, r2 @ write back cpsr (may have caused a mode switch)
112 mov sp, r3 @ restore stack pointer
113 ldmfd sp!, {r4-r12, lr} @ restore registers
114 bx lr @ return (hopefully thumb-safe!)
115
116 ASM_PFX(CPSRRead):
117 mrs r0, cpsr
118 bx lr
119
120 ASM_FUNCTION_REMOVE_IF_UNREFERENCED