ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm

   1 //------------------------------------------------------------------------------
   2 //
   3 // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4 // Copyright (c) 2011-2012, ARM Limited. All rights reserved.
   5 //
   6 // This program and the accompanying materials
   7 // are licensed and made available under the terms and conditions of the BSD License
   8 // which accompanies this distribution.  The full text of the license may be found at
   9 // http://opensource.org/licenses/bsd-license.php
  10 //
  11 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 //
  14 //------------------------------------------------------------------------------
  15
  16 #include <AsmMacroIoLib.h>
  17
  18     INCLUDE AsmMacroIoLib.inc
  19
  20 #ifdef ARM_CPU_ARMv6
  21 // No memory barriers for ARMv6
  22 #define isb
  23 #define dsb
  24 #endif
  25
  26     EXPORT Cp15IdCode
  27     EXPORT Cp15CacheInfo
  28     EXPORT ArmGetInterruptState
  29     EXPORT ArmGetFiqState
  30     EXPORT ArmGetTTBR0BaseAddress
  31     EXPORT ArmSetTTBR0
  32     EXPORT ArmSetDomainAccessControl
  33     EXPORT CPSRMaskInsert
  34     EXPORT CPSRRead
  35     EXPORT ArmReadCpacr
  36     EXPORT ArmWriteCpacr
  37     EXPORT ArmWriteAuxCr
  38     EXPORT ArmReadAuxCr
  39     EXPORT ArmInvalidateTlb
  40     EXPORT ArmUpdateTranslationTableEntry
  41     EXPORT ArmReadNsacr
  42     EXPORT ArmWriteNsacr
  43     EXPORT ArmReadScr
  44     EXPORT ArmWriteScr
  45     EXPORT ArmReadMVBar
  46     EXPORT ArmWriteMVBar
  47     EXPORT ArmCallWFE
  48     EXPORT ArmCallSEV
  49     EXPORT ArmReadSctlr
  50
  51     AREA ArmLibSupport, CODE, READONLY
  52
  53 Cp15IdCode
  54   mrc     p15,0,R0,c0,c0,0
  55   bx      LR
  56
  57 Cp15CacheInfo
  58   mrc     p15,0,R0,c0,c0,1
  59   bx      LR
  60
  61 ArmGetInterruptState
  62   mrs     R0,CPSR
  63   tst     R0,#0x80      // Check if IRQ is enabled.
  64   moveq   R0,#1
  65   movne   R0,#0
  66   bx      LR
  67
  68 ArmGetFiqState
  69   mrs     R0,CPSR
  70   tst     R0,#0x40      // Check if FIQ is enabled.
  71   moveq   R0,#1
  72   movne   R0,#0
  73   bx      LR
  74
  75 ArmSetDomainAccessControl
  76   mcr     p15,0,r0,c3,c0,0
  77   bx      lr
  78
  79 CPSRMaskInsert    // on entry, r0 is the mask and r1 is the field to insert
  80   stmfd   sp!, {r4-r12, lr} // save all the banked registers
  81   mov     r3, sp            // copy the stack pointer into a non-banked register
  82   mrs     r2, cpsr          // read the cpsr
  83   bic     r2, r2, r0        // clear mask in the cpsr
  84   and     r1, r1, r0        // clear bits outside the mask in the input
  85   orr     r2, r2, r1        // set field
  86   msr     cpsr_cxsf, r2     // write back cpsr (may have caused a mode switch)
  87   isb
  88   mov     sp, r3            // restore stack pointer
  89   ldmfd   sp!, {r4-r12, lr} // restore registers
  90   bx      lr                // return (hopefully thumb-safe!)             // return (hopefully thumb-safe!)
  91
  92 CPSRRead
  93   mrs     r0, cpsr
  94   bx      lr
  95
  96 ArmReadCpacr
  97   mrc     p15, 0, r0, c1, c0, 2
  98   bx      lr
  99
 100 ArmWriteCpacr
 101   mcr     p15, 0, r0, c1, c0, 2
 102   isb
 103   bx      lr
 104
 105 ArmWriteAuxCr
 106   mcr     p15, 0, r0, c1, c0, 1
 107   bx      lr
 108
 109 ArmReadAuxCr
 110   mrc     p15, 0, r0, c1, c0, 1
 111   bx      lr
 112
 113 ArmSetTTBR0
 114   mcr     p15,0,r0,c2,c0,0
 115   isb
 116   bx      lr
 117
 118 ArmGetTTBR0BaseAddress
 119   mrc     p15,0,r0,c2,c0,0
 120   LoadConstantToReg(0xFFFFC000, r1)
 121   and     r0, r0, r1
 122   isb
 123   bx      lr
 124
 125 //
 126 //VOID
 127 //ArmUpdateTranslationTableEntry (
 128 //  IN VOID  *TranslationTableEntry  // R0
 129 //  IN VOID  *MVA                    // R1
 130 //  );
 131 ArmUpdateTranslationTableEntry
 132   mcr     p15,0,R0,c7,c14,1     // DCCIMVAC Clean data cache by MVA
 133   dsb
 134   mcr     p15,0,R1,c8,c7,1      // TLBIMVA TLB Invalidate MVA
 135   mcr     p15,0,R9,c7,c5,6      // BPIALL Invalidate Branch predictor array. R9 == NoOp
 136   dsb
 137   isb
 138   bx      lr
 139
 140 ArmInvalidateTlb
 141   mov     r0,#0
 142   mcr     p15,0,r0,c8,c7,0
 143   mcr     p15,0,R9,c7,c5,6      // BPIALL Invalidate Branch predictor array. R9 == NoOp
 144   dsb
 145   isb
 146   bx      lr
 147
 148 ArmReadNsacr
 149   mrc     p15, 0, r0, c1, c1, 2
 150   bx      lr
 151
 152 ArmWriteNsacr
 153   mcr     p15, 0, r0, c1, c1, 2
 154   bx      lr
 155
 156 ArmReadScr
 157   mrc     p15, 0, r0, c1, c1, 0
 158   bx      lr
 159
 160 ArmWriteScr
 161   mcr     p15, 0, r0, c1, c1, 0
 162   bx      lr
 163
 164 ArmReadMVBar
 165   mrc     p15, 0, r0, c12, c0, 1
 166   bx      lr
 167
 168 ArmWriteMVBar
 169   mcr     p15, 0, r0, c12, c0, 1
 170   bx      lr
 171
 172 ArmCallWFE
 173   wfe
 174   blx   lr
 175
 176 ArmCallSEV
 177   sev
 178   blx   lr
 179
 180 ArmReadSctlr
 181   mrc     p15, 0, R0, c1, c0, 0      // Read SCTLR into R0 (Read control register configuration data)
 182   bx      lr
 183
 184   END