ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm

   1 //------------------------------------------------------------------------------
   2 //
   3 // Copyright (c) 2008-2009 Apple Inc. All rights reserved.
   4 //
   5 // All rights reserved. This program and the accompanying materials
   6 // are licensed and made available under the terms and conditions of the BSD License
   7 // which accompanies this distribution.  The full text of the license may be found at
   8 // http://opensource.org/licenses/bsd-license.php
   9 //
  10 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 //
  13 //------------------------------------------------------------------------------
  14
  15
  16     EXPORT  Cp15IdCode
  17     EXPORT  Cp15CacheInfo
  18     EXPORT  ArmEnableInterrupts
  19     EXPORT  ArmDisableInterrupts
  20     EXPORT  ArmGetInterruptState
  21     EXPORT  ArmInvalidateTlb
  22     EXPORT  ArmSetTranslationTableBaseAddress
  23     EXPORT  ArmSetDomainAccessControl
  24     EXPORT  CPSRMaskInsert
  25     EXPORT  CPSRRead
  26
  27     AREA ArmLibSupport, CODE, READONLY
  28
  29 Cp15IdCode
  30   mrc     p15,0,R0,c0,c0,0
  31   bx      LR
  32
  33 Cp15CacheInfo
  34   mrc     p15,0,R0,c0,c0,1
  35   bx      LR
  36
  37 ArmEnableInterrupts
  38         mrs     R0,CPSR
  39         bic     R0,R0,#0x80             ;Enable IRQ interrupts
  40         msr     CPSR_c,R0
  41         bx      LR
  42
  43 ArmDisableInterrupts
  44         mrs     R0,CPSR
  45         orr     R1,R0,#0x80             ;Disable IRQ interrupts
  46         msr     CPSR_c,R1
  47   tst     R0,#0x80
  48   moveq   R0,#1
  49   movne   R0,#0
  50         bx      LR
  51
  52 ArmGetInterruptState
  53         mrs     R0,CPSR
  54         tst     R0,#0x80            ;Check if IRQ is enabled.
  55         moveq   R0,#1
  56         movne   R0,#0
  57         bx      LR
  58
  59 ArmInvalidateTlb
  60   mov     r0,#0
  61   mcr     p15,0,r0,c8,c7,0
  62   bx      lr
  63
  64 ArmSetTranslationTableBaseAddress
  65   mcr     p15,0,r0,c2,c0,0
  66   bx      lr
  67
  68 ArmSetDomainAccessControl
  69   mcr     p15,0,r0,c3,c0,0
  70   bx      lr
  71
  72 CPSRMaskInsert              ; on entry, r0 is the mask and r1 is the field to insert
  73   stmfd   sp!, {r4-r12, lr} ; save all the banked registers
  74   mov     r3, sp            ; copy the stack pointer into a non-banked register
  75   mrs     r2, cpsr          ; read the cpsr
  76   bic     r2, r2, r0        ; clear mask in the cpsr
  77   and     r1, r1, r0        ; clear bits outside the mask in the input
  78   orr     r2, r2, r1        ; set field
  79   msr     cpsr_cxsf, r2     ; write back cpsr (may have caused a mode switch)
  80   mov     sp, r3            ; restore stack pointer
  81   ldmfd   sp!, {r4-r12, lr} ; restore registers
  82   bx      lr                ; return (hopefully thumb-safe!)
  83
  84 CPSRRead
  85   mrs     r0, cpsr
  86   bx      lr
  87
  88   END
  89
  90