2 * File managing the MMU for ARMv8 architecture
4 * Copyright (c) 2011-2014, ARM Limited. All rights reserved.
5 * Copyright (c) 2016, Linaro Limited. All rights reserved.
7 * This program and the accompanying materials
8 * are licensed and made available under the terms and conditions of the BSD License
9 * which accompanies this distribution. The full text of the license may be found at
10 * http://opensource.org/licenses/bsd-license.php
12 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
18 #include <Chipset/AArch64.h>
19 #include <Library/BaseMemoryLib.h>
20 #include <Library/CacheMaintenanceLib.h>
21 #include <Library/MemoryAllocationLib.h>
22 #include <Library/ArmLib.h>
23 #include <Library/ArmMmuLib.h>
24 #include <Library/BaseLib.h>
25 #include <Library/DebugLib.h>
27 // We use this index definition to define an invalid block entry
28 #define TT_ATTR_INDX_INVALID ((UINT32)~0)
32 ArmMemoryAttributeToPageAttribute (
33 IN ARM_MEMORY_REGION_ATTRIBUTES Attributes
37 case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
:
38 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK
:
39 return TT_ATTR_INDX_MEMORY_WRITE_BACK
| TT_SH_INNER_SHAREABLE
;
41 case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH
:
42 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH
:
43 return TT_ATTR_INDX_MEMORY_WRITE_THROUGH
| TT_SH_INNER_SHAREABLE
;
45 // Uncached and device mappings are treated as outer shareable by default,
46 case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
:
47 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED
:
48 return TT_ATTR_INDX_MEMORY_NON_CACHEABLE
;
52 case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
:
53 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE
:
54 if (ArmReadCurrentEL () == AARCH64_EL2
)
55 return TT_ATTR_INDX_DEVICE_MEMORY
| TT_XN_MASK
;
57 return TT_ATTR_INDX_DEVICE_MEMORY
| TT_UXN_MASK
| TT_PXN_MASK
;
62 PageAttributeToGcdAttribute (
63 IN UINT64 PageAttributes
68 switch (PageAttributes
& TT_ATTR_INDX_MASK
) {
69 case TT_ATTR_INDX_DEVICE_MEMORY
:
70 GcdAttributes
= EFI_MEMORY_UC
;
72 case TT_ATTR_INDX_MEMORY_NON_CACHEABLE
:
73 GcdAttributes
= EFI_MEMORY_WC
;
75 case TT_ATTR_INDX_MEMORY_WRITE_THROUGH
:
76 GcdAttributes
= EFI_MEMORY_WT
;
78 case TT_ATTR_INDX_MEMORY_WRITE_BACK
:
79 GcdAttributes
= EFI_MEMORY_WB
;
82 DEBUG ((EFI_D_ERROR
, "PageAttributeToGcdAttribute: PageAttributes:0x%lX not supported.\n", PageAttributes
));
84 // The Global Coherency Domain (GCD) value is defined as a bit set.
85 // Returning 0 means no attribute has been set.
89 // Determine protection attributes
90 if (((PageAttributes
& TT_AP_MASK
) == TT_AP_NO_RO
) || ((PageAttributes
& TT_AP_MASK
) == TT_AP_RO_RO
)) {
91 // Read only cases map to write-protect
92 GcdAttributes
|= EFI_MEMORY_WP
;
95 // Process eXecute Never attribute
96 if ((PageAttributes
& (TT_PXN_MASK
| TT_UXN_MASK
)) != 0 ) {
97 GcdAttributes
|= EFI_MEMORY_XP
;
100 return GcdAttributes
;
103 ARM_MEMORY_REGION_ATTRIBUTES
104 GcdAttributeToArmAttribute (
105 IN UINT64 GcdAttributes
108 switch (GcdAttributes
& 0xFF) {
110 return ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
;
112 return ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
;
114 return ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH
;
116 return ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
;
118 DEBUG ((EFI_D_ERROR
, "GcdAttributeToArmAttribute: 0x%lX attributes is not supported.\n", GcdAttributes
));
120 return ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
;
125 #define BITS_PER_LEVEL 9
128 GetRootTranslationTableInfo (
130 OUT UINTN
*TableLevel
,
131 OUT UINTN
*TableEntryCount
134 // Get the level of the root table
136 *TableLevel
= (T0SZ
- MIN_T0SZ
) / BITS_PER_LEVEL
;
139 if (TableEntryCount
) {
140 *TableEntryCount
= 1UL << (BITS_PER_LEVEL
- (T0SZ
- MIN_T0SZ
) % BITS_PER_LEVEL
);
151 if (!ArmMmuEnabled ()) {
154 ArmReplaceLiveTranslationEntry (Entry
, Value
);
160 LookupAddresstoRootTable (
161 IN UINT64 MaxAddress
,
163 OUT UINTN
*TableEntryCount
168 // Check the parameters are not NULL
169 ASSERT ((T0SZ
!= NULL
) && (TableEntryCount
!= NULL
));
171 // Look for the highest bit set in MaxAddress
172 for (TopBit
= 63; TopBit
!= 0; TopBit
--) {
173 if ((1ULL << TopBit
) & MaxAddress
) {
174 // MaxAddress top bit is found
179 ASSERT (TopBit
!= 0);
181 // Calculate T0SZ from the top bit of the MaxAddress
184 // Get the Table info from T0SZ
185 GetRootTranslationTableInfo (*T0SZ
, NULL
, TableEntryCount
);
190 GetBlockEntryListFromAddress (
191 IN UINT64
*RootTable
,
192 IN UINT64 RegionStart
,
193 OUT UINTN
*TableLevel
,
194 IN OUT UINT64
*BlockEntrySize
,
195 OUT UINT64
**LastBlockEntry
198 UINTN RootTableLevel
;
199 UINTN RootTableEntryCount
;
200 UINT64
*TranslationTable
;
202 UINT64
*SubTableBlockEntry
;
203 UINT64 BlockEntryAddress
;
204 UINTN BaseAddressAlignment
;
210 UINT64 TableAttributes
;
212 // Initialize variable
215 // Ensure the parameters are valid
216 if (!(TableLevel
&& BlockEntrySize
&& LastBlockEntry
)) {
217 ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER
);
221 // Ensure the Region is aligned on 4KB boundary
222 if ((RegionStart
& (SIZE_4KB
- 1)) != 0) {
223 ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER
);
227 // Ensure the required size is aligned on 4KB boundary and not 0
228 if ((*BlockEntrySize
& (SIZE_4KB
- 1)) != 0 || *BlockEntrySize
== 0) {
229 ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER
);
233 T0SZ
= ArmGetTCR () & TCR_T0SZ_MASK
;
234 // Get the Table info from T0SZ
235 GetRootTranslationTableInfo (T0SZ
, &RootTableLevel
, &RootTableEntryCount
);
237 // If the start address is 0x0 then we use the size of the region to identify the alignment
238 if (RegionStart
== 0) {
239 // Identify the highest possible alignment for the Region Size
240 BaseAddressAlignment
= LowBitSet64 (*BlockEntrySize
);
242 // Identify the highest possible alignment for the Base Address
243 BaseAddressAlignment
= LowBitSet64 (RegionStart
);
246 // Identify the Page Level the RegionStart must belong to. Note that PageLevel
247 // should be at least 1 since block translations are not supported at level 0
248 PageLevel
= MAX (3 - ((BaseAddressAlignment
- 12) / 9), 1);
250 // If the required size is smaller than the current block size then we need to go to the page below.
251 // The PageLevel was calculated on the Base Address alignment but did not take in account the alignment
252 // of the allocation size
253 while (*BlockEntrySize
< TT_BLOCK_ENTRY_SIZE_AT_LEVEL (PageLevel
)) {
254 // It does not fit so we need to go a page level above
259 // Get the Table Descriptor for the corresponding PageLevel. We need to decompose RegionStart to get appropriate entries
262 TranslationTable
= RootTable
;
263 for (IndexLevel
= RootTableLevel
; IndexLevel
<= PageLevel
; IndexLevel
++) {
264 BlockEntry
= (UINT64
*)TT_GET_ENTRY_FOR_ADDRESS (TranslationTable
, IndexLevel
, RegionStart
);
266 if ((IndexLevel
!= 3) && ((*BlockEntry
& TT_TYPE_MASK
) == TT_TYPE_TABLE_ENTRY
)) {
267 // Go to the next table
268 TranslationTable
= (UINT64
*)(*BlockEntry
& TT_ADDRESS_MASK_DESCRIPTION_TABLE
);
270 // If we are at the last level then update the last level to next level
271 if (IndexLevel
== PageLevel
) {
272 // Enter the next level
275 } else if ((*BlockEntry
& TT_TYPE_MASK
) == TT_TYPE_BLOCK_ENTRY
) {
276 // If we are not at the last level then we need to split this BlockEntry
277 if (IndexLevel
!= PageLevel
) {
278 // Retrieve the attributes from the block entry
279 Attributes
= *BlockEntry
& TT_ATTRIBUTES_MASK
;
281 // Convert the block entry attributes into Table descriptor attributes
282 TableAttributes
= TT_TABLE_AP_NO_PERMISSION
;
283 if (Attributes
& TT_NS
) {
284 TableAttributes
= TT_TABLE_NS
;
287 // Get the address corresponding at this entry
288 BlockEntryAddress
= RegionStart
;
289 BlockEntryAddress
= BlockEntryAddress
>> TT_ADDRESS_OFFSET_AT_LEVEL(IndexLevel
);
290 // Shift back to right to set zero before the effective address
291 BlockEntryAddress
= BlockEntryAddress
<< TT_ADDRESS_OFFSET_AT_LEVEL(IndexLevel
);
293 // Set the correct entry type for the next page level
294 if ((IndexLevel
+ 1) == 3) {
295 Attributes
|= TT_TYPE_BLOCK_ENTRY_LEVEL3
;
297 Attributes
|= TT_TYPE_BLOCK_ENTRY
;
300 // Create a new translation table
301 TranslationTable
= AllocatePages (1);
302 if (TranslationTable
== NULL
) {
306 // Populate the newly created lower level table
307 SubTableBlockEntry
= TranslationTable
;
308 for (Index
= 0; Index
< TT_ENTRY_COUNT
; Index
++) {
309 *SubTableBlockEntry
= Attributes
| (BlockEntryAddress
+ (Index
<< TT_ADDRESS_OFFSET_AT_LEVEL(IndexLevel
+ 1)));
310 SubTableBlockEntry
++;
313 // Fill the BlockEntry with the new TranslationTable
314 ReplaceLiveEntry (BlockEntry
,
315 ((UINTN
)TranslationTable
& TT_ADDRESS_MASK_DESCRIPTION_TABLE
) | TableAttributes
| TT_TYPE_TABLE_ENTRY
);
318 if (IndexLevel
!= PageLevel
) {
320 // Case when we have an Invalid Entry and we are at a page level above of the one targetted.
323 // Create a new translation table
324 TranslationTable
= AllocatePages (1);
325 if (TranslationTable
== NULL
) {
329 ZeroMem (TranslationTable
, TT_ENTRY_COUNT
* sizeof(UINT64
));
331 // Fill the new BlockEntry with the TranslationTable
332 *BlockEntry
= ((UINTN
)TranslationTable
& TT_ADDRESS_MASK_DESCRIPTION_TABLE
) | TT_TYPE_TABLE_ENTRY
;
337 // Expose the found PageLevel to the caller
338 *TableLevel
= PageLevel
;
340 // Now, we have the Table Level we can get the Block Size associated to this table
341 *BlockEntrySize
= TT_BLOCK_ENTRY_SIZE_AT_LEVEL (PageLevel
);
343 // The last block of the root table depends on the number of entry in this table,
344 // otherwise it is always the (TT_ENTRY_COUNT - 1)th entry in the table.
345 *LastBlockEntry
= TT_LAST_BLOCK_ADDRESS(TranslationTable
,
346 (PageLevel
== RootTableLevel
) ? RootTableEntryCount
: TT_ENTRY_COUNT
);
353 UpdateRegionMapping (
354 IN UINT64
*RootTable
,
355 IN UINT64 RegionStart
,
356 IN UINT64 RegionLength
,
357 IN UINT64 Attributes
,
358 IN UINT64 BlockEntryMask
363 UINT64
*LastBlockEntry
;
364 UINT64 BlockEntrySize
;
367 // Ensure the Length is aligned on 4KB boundary
368 if ((RegionLength
== 0) || ((RegionLength
& (SIZE_4KB
- 1)) != 0)) {
369 ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER
);
370 return RETURN_INVALID_PARAMETER
;
374 // Get the first Block Entry that matches the Virtual Address and also the information on the Table Descriptor
375 // such as the the size of the Block Entry and the address of the last BlockEntry of the Table Descriptor
376 BlockEntrySize
= RegionLength
;
377 BlockEntry
= GetBlockEntryListFromAddress (RootTable
, RegionStart
, &TableLevel
, &BlockEntrySize
, &LastBlockEntry
);
378 if (BlockEntry
== NULL
) {
379 // GetBlockEntryListFromAddress() return NULL when it fails to allocate new pages from the Translation Tables
380 return RETURN_OUT_OF_RESOURCES
;
383 if (TableLevel
!= 3) {
384 Type
= TT_TYPE_BLOCK_ENTRY
;
386 Type
= TT_TYPE_BLOCK_ENTRY_LEVEL3
;
390 // Fill the Block Entry with attribute and output block address
391 *BlockEntry
&= BlockEntryMask
;
392 *BlockEntry
|= (RegionStart
& TT_ADDRESS_MASK_BLOCK_ENTRY
) | Attributes
| Type
;
394 // Go to the next BlockEntry
395 RegionStart
+= BlockEntrySize
;
396 RegionLength
-= BlockEntrySize
;
399 // Break the inner loop when next block is a table
400 // Rerun GetBlockEntryListFromAddress to avoid page table memory leak
401 if (TableLevel
!= 3 &&
402 (*BlockEntry
& TT_TYPE_MASK
) == TT_TYPE_TABLE_ENTRY
) {
405 } while ((RegionLength
>= BlockEntrySize
) && (BlockEntry
<= LastBlockEntry
));
406 } while (RegionLength
!= 0);
408 return RETURN_SUCCESS
;
413 FillTranslationTable (
414 IN UINT64
*RootTable
,
415 IN ARM_MEMORY_REGION_DESCRIPTOR
*MemoryRegion
418 return UpdateRegionMapping (
420 MemoryRegion
->VirtualBase
,
421 MemoryRegion
->Length
,
422 ArmMemoryAttributeToPageAttribute (MemoryRegion
->Attributes
) | TT_AF
,
428 SetMemoryAttributes (
429 IN EFI_PHYSICAL_ADDRESS BaseAddress
,
431 IN UINT64 Attributes
,
432 IN EFI_PHYSICAL_ADDRESS VirtualMask
435 RETURN_STATUS Status
;
436 ARM_MEMORY_REGION_DESCRIPTOR MemoryRegion
;
437 UINT64
*TranslationTable
;
439 MemoryRegion
.PhysicalBase
= BaseAddress
;
440 MemoryRegion
.VirtualBase
= BaseAddress
;
441 MemoryRegion
.Length
= Length
;
442 MemoryRegion
.Attributes
= GcdAttributeToArmAttribute (Attributes
);
444 TranslationTable
= ArmGetTTBR0BaseAddress ();
446 Status
= FillTranslationTable (TranslationTable
, &MemoryRegion
);
447 if (RETURN_ERROR (Status
)) {
451 // Invalidate all TLB entries so changes are synced
454 return RETURN_SUCCESS
;
459 SetMemoryRegionAttribute (
460 IN EFI_PHYSICAL_ADDRESS BaseAddress
,
462 IN UINT64 Attributes
,
463 IN UINT64 BlockEntryMask
466 RETURN_STATUS Status
;
469 RootTable
= ArmGetTTBR0BaseAddress ();
471 Status
= UpdateRegionMapping (RootTable
, BaseAddress
, Length
, Attributes
, BlockEntryMask
);
472 if (RETURN_ERROR (Status
)) {
476 // Invalidate all TLB entries so changes are synced
479 return RETURN_SUCCESS
;
483 ArmSetMemoryRegionNoExec (
484 IN EFI_PHYSICAL_ADDRESS BaseAddress
,
490 if (ArmReadCurrentEL () == AARCH64_EL1
) {
491 Val
= TT_PXN_MASK
| TT_UXN_MASK
;
496 return SetMemoryRegionAttribute (
500 ~TT_ADDRESS_MASK_BLOCK_ENTRY
);
504 ArmClearMemoryRegionNoExec (
505 IN EFI_PHYSICAL_ADDRESS BaseAddress
,
511 // XN maps to UXN in the EL1&0 translation regime
512 Mask
= ~(TT_ADDRESS_MASK_BLOCK_ENTRY
| TT_PXN_MASK
| TT_XN_MASK
);
514 return SetMemoryRegionAttribute (
522 ArmSetMemoryRegionReadOnly (
523 IN EFI_PHYSICAL_ADDRESS BaseAddress
,
527 return SetMemoryRegionAttribute (
531 ~TT_ADDRESS_MASK_BLOCK_ENTRY
);
535 ArmClearMemoryRegionReadOnly (
536 IN EFI_PHYSICAL_ADDRESS BaseAddress
,
540 return SetMemoryRegionAttribute (
544 ~(TT_ADDRESS_MASK_BLOCK_ENTRY
| TT_AP_MASK
));
550 IN ARM_MEMORY_REGION_DESCRIPTOR
*MemoryTable
,
551 OUT VOID
**TranslationTableBase OPTIONAL
,
552 OUT UINTN
*TranslationTableSize OPTIONAL
555 VOID
* TranslationTable
;
556 VOID
* TranslationTableBuffer
;
557 UINT32 TranslationTableAttribute
;
558 ARM_MEMORY_REGION_DESCRIPTOR
*MemoryTableEntry
;
562 UINTN RootTableEntryCount
;
563 UINTN RootTableEntrySize
;
565 RETURN_STATUS Status
;
567 if(MemoryTable
== NULL
) {
568 ASSERT (MemoryTable
!= NULL
);
569 return RETURN_INVALID_PARAMETER
;
572 // Identify the highest address of the memory table
573 MaxAddress
= MemoryTable
->PhysicalBase
+ MemoryTable
->Length
- 1;
574 MemoryTableEntry
= MemoryTable
;
575 while (MemoryTableEntry
->Length
!= 0) {
576 TopAddress
= MemoryTableEntry
->PhysicalBase
+ MemoryTableEntry
->Length
- 1;
577 if (TopAddress
> MaxAddress
) {
578 MaxAddress
= TopAddress
;
583 // Lookup the Table Level to get the information
584 LookupAddresstoRootTable (MaxAddress
, &T0SZ
, &RootTableEntryCount
);
587 // Set TCR that allows us to retrieve T0SZ in the subsequent functions
589 // Ideally we will be running at EL2, but should support EL1 as well.
590 // UEFI should not run at EL3.
591 if (ArmReadCurrentEL () == AARCH64_EL2
) {
592 //Note: Bits 23 and 31 are reserved(RES1) bits in TCR_EL2
593 TCR
= T0SZ
| (1UL << 31) | (1UL << 23) | TCR_TG0_4KB
;
595 // Set the Physical Address Size using MaxAddress
596 if (MaxAddress
< SIZE_4GB
) {
598 } else if (MaxAddress
< SIZE_64GB
) {
600 } else if (MaxAddress
< SIZE_1TB
) {
602 } else if (MaxAddress
< SIZE_4TB
) {
604 } else if (MaxAddress
< SIZE_16TB
) {
606 } else if (MaxAddress
< SIZE_256TB
) {
609 DEBUG ((EFI_D_ERROR
, "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n", MaxAddress
));
610 ASSERT (0); // Bigger than 48-bit memory space are not supported
611 return RETURN_UNSUPPORTED
;
613 } else if (ArmReadCurrentEL () == AARCH64_EL1
) {
614 // Due to Cortex-A57 erratum #822227 we must set TG1[1] == 1, regardless of EPD1.
615 TCR
= T0SZ
| TCR_TG0_4KB
| TCR_TG1_4KB
| TCR_EPD1
;
617 // Set the Physical Address Size using MaxAddress
618 if (MaxAddress
< SIZE_4GB
) {
620 } else if (MaxAddress
< SIZE_64GB
) {
622 } else if (MaxAddress
< SIZE_1TB
) {
624 } else if (MaxAddress
< SIZE_4TB
) {
626 } else if (MaxAddress
< SIZE_16TB
) {
628 } else if (MaxAddress
< SIZE_256TB
) {
629 TCR
|= TCR_IPS_256TB
;
631 DEBUG ((EFI_D_ERROR
, "ArmConfigureMmu: The MaxAddress 0x%lX is not supported by this MMU configuration.\n", MaxAddress
));
632 ASSERT (0); // Bigger than 48-bit memory space are not supported
633 return RETURN_UNSUPPORTED
;
636 ASSERT (0); // UEFI is only expected to run at EL2 and EL1, not EL3.
637 return RETURN_UNSUPPORTED
;
643 // Allocate pages for translation table. Pool allocations are 8 byte aligned,
644 // but we may require a higher alignment based on the size of the root table.
645 RootTableEntrySize
= RootTableEntryCount
* sizeof(UINT64
);
646 if (RootTableEntrySize
< EFI_PAGE_SIZE
/ 2) {
647 TranslationTableBuffer
= AllocatePool (2 * RootTableEntrySize
- 8);
649 // Naturally align the root table. Preserves possible NULL value
651 TranslationTable
= (VOID
*)((UINTN
)(TranslationTableBuffer
- 1) | (RootTableEntrySize
- 1)) + 1;
653 TranslationTable
= AllocatePages (1);
654 TranslationTableBuffer
= NULL
;
656 if (TranslationTable
== NULL
) {
657 return RETURN_OUT_OF_RESOURCES
;
659 // We set TTBR0 just after allocating the table to retrieve its location from the subsequent
660 // functions without needing to pass this value across the functions. The MMU is only enabled
661 // after the translation tables are populated.
662 ArmSetTTBR0 (TranslationTable
);
664 if (TranslationTableBase
!= NULL
) {
665 *TranslationTableBase
= TranslationTable
;
668 if (TranslationTableSize
!= NULL
) {
669 *TranslationTableSize
= RootTableEntrySize
;
672 ZeroMem (TranslationTable
, RootTableEntrySize
);
674 // Disable MMU and caches. ArmDisableMmu() also invalidates the TLBs
676 ArmDisableDataCache ();
677 ArmDisableInstructionCache ();
679 // Make sure nothing sneaked into the cache
680 ArmCleanInvalidateDataCache ();
681 ArmInvalidateInstructionCache ();
683 TranslationTableAttribute
= TT_ATTR_INDX_INVALID
;
684 while (MemoryTable
->Length
!= 0) {
685 // Find the memory attribute for the Translation Table
686 if (((UINTN
)TranslationTable
>= MemoryTable
->PhysicalBase
) &&
687 ((UINTN
)TranslationTable
<= MemoryTable
->PhysicalBase
- 1 + MemoryTable
->Length
)) {
688 TranslationTableAttribute
= MemoryTable
->Attributes
;
691 Status
= FillTranslationTable (TranslationTable
, MemoryTable
);
692 if (RETURN_ERROR (Status
)) {
693 goto FREE_TRANSLATION_TABLE
;
698 // Translate the Memory Attributes into Translation Table Register Attributes
699 if ((TranslationTableAttribute
== ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
) ||
700 (TranslationTableAttribute
== ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED
)) {
701 TCR
|= TCR_SH_NON_SHAREABLE
| TCR_RGN_OUTER_NON_CACHEABLE
| TCR_RGN_INNER_NON_CACHEABLE
;
702 } else if ((TranslationTableAttribute
== ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
) ||
703 (TranslationTableAttribute
== ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK
)) {
704 TCR
|= TCR_SH_INNER_SHAREABLE
| TCR_RGN_OUTER_WRITE_BACK_ALLOC
| TCR_RGN_INNER_WRITE_BACK_ALLOC
;
705 } else if ((TranslationTableAttribute
== ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH
) ||
706 (TranslationTableAttribute
== ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH
)) {
707 TCR
|= TCR_SH_NON_SHAREABLE
| TCR_RGN_OUTER_WRITE_THROUGH
| TCR_RGN_INNER_WRITE_THROUGH
;
709 // If we failed to find a mapping that contains the root translation table then it probably means the translation table
710 // is not mapped in the given memory map.
712 Status
= RETURN_UNSUPPORTED
;
713 goto FREE_TRANSLATION_TABLE
;
716 // Set again TCR after getting the Translation Table attributes
719 ArmSetMAIR (MAIR_ATTR(TT_ATTR_INDX_DEVICE_MEMORY
, MAIR_ATTR_DEVICE_MEMORY
) | // mapped to EFI_MEMORY_UC
720 MAIR_ATTR(TT_ATTR_INDX_MEMORY_NON_CACHEABLE
, MAIR_ATTR_NORMAL_MEMORY_NON_CACHEABLE
) | // mapped to EFI_MEMORY_WC
721 MAIR_ATTR(TT_ATTR_INDX_MEMORY_WRITE_THROUGH
, MAIR_ATTR_NORMAL_MEMORY_WRITE_THROUGH
) | // mapped to EFI_MEMORY_WT
722 MAIR_ATTR(TT_ATTR_INDX_MEMORY_WRITE_BACK
, MAIR_ATTR_NORMAL_MEMORY_WRITE_BACK
)); // mapped to EFI_MEMORY_WB
724 ArmDisableAlignmentCheck ();
725 ArmEnableInstructionCache ();
726 ArmEnableDataCache ();
729 return RETURN_SUCCESS
;
731 FREE_TRANSLATION_TABLE
:
732 if (TranslationTableBuffer
!= NULL
) {
733 FreePool (TranslationTableBuffer
);
735 FreePages (TranslationTable
, 1);
742 ArmMmuBaseLibConstructor (
746 extern UINT32 ArmReplaceLiveTranslationEntrySize
;
749 // The ArmReplaceLiveTranslationEntry () helper function may be invoked
750 // with the MMU off so we have to ensure that it gets cleaned to the PoC
752 WriteBackDataCacheRange (ArmReplaceLiveTranslationEntry
,
753 ArmReplaceLiveTranslationEntrySize
);
755 return RETURN_SUCCESS
;