2 * File managing the MMU for ARMv7 architecture
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4 * Copyright (c) 2011-2016, ARM Limited. All rights reserved.
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6 * This program and the accompanying materials
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7 * are licensed and made available under the terms and conditions of the BSD License
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8 * which accompanies this distribution. The full text of the license may be found at
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9 * http://opensource.org/licenses/bsd-license.php
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11 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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12 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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17 #include <Chipset/ArmV7.h>
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18 #include <Library/BaseMemoryLib.h>
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19 #include <Library/CacheMaintenanceLib.h>
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20 #include <Library/MemoryAllocationLib.h>
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21 #include <Library/ArmLib.h>
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22 #include <Library/BaseLib.h>
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23 #include <Library/DebugLib.h>
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24 #include <Library/PcdLib.h>
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26 #define ID_MMFR0_SHARELVL_SHIFT 12
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27 #define ID_MMFR0_SHARELVL_MASK 0xf
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28 #define ID_MMFR0_SHARELVL_ONE 0
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29 #define ID_MMFR0_SHARELVL_TWO 1
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31 #define ID_MMFR0_INNERSHR_SHIFT 28
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32 #define ID_MMFR0_INNERSHR_MASK 0xf
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33 #define ID_MMFR0_OUTERSHR_SHIFT 8
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34 #define ID_MMFR0_OUTERSHR_MASK 0xf
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36 #define ID_MMFR0_SHR_IMP_UNCACHED 0
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37 #define ID_MMFR0_SHR_IMP_HW_COHERENT 1
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38 #define ID_MMFR0_SHR_IGNORED 0xf
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40 #define __EFI_MEMORY_RWX 0 // no restrictions
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42 #define CACHE_ATTRIBUTE_MASK (EFI_MEMORY_UC | \
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57 ArmHasMpExtensions (
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62 ConvertSectionAttributesToPageAttributes (
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63 IN UINT32 SectionAttributes,
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64 IN BOOLEAN IsLargePage
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67 UINT32 PageAttributes;
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70 PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_CACHE_POLICY (SectionAttributes, IsLargePage);
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71 PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_AP (SectionAttributes);
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72 PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_XN (SectionAttributes, IsLargePage);
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73 PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_NG (SectionAttributes);
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74 PageAttributes |= TT_DESCRIPTOR_CONVERT_TO_PAGE_S (SectionAttributes);
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76 return PageAttributes;
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81 PreferNonshareableMemory (
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88 if (FeaturePcdGet (PcdNormalMemoryNonshareableOverride)) {
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93 // Check whether the innermost level of shareability (the level we will use
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94 // by default to map normal memory) is implemented with hardware coherency
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95 // support. Otherwise, revert to mapping as non-shareable.
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97 Mmfr = ArmReadIdMmfr0 ();
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98 switch ((Mmfr >> ID_MMFR0_SHARELVL_SHIFT) & ID_MMFR0_SHARELVL_MASK) {
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99 case ID_MMFR0_SHARELVL_ONE:
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100 // one level of shareability
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101 Val = (Mmfr >> ID_MMFR0_OUTERSHR_SHIFT) & ID_MMFR0_OUTERSHR_MASK;
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103 case ID_MMFR0_SHARELVL_TWO:
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104 // two levels of shareability
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105 Val = (Mmfr >> ID_MMFR0_INNERSHR_SHIFT) & ID_MMFR0_INNERSHR_MASK;
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108 // unexpected value -> shareable is the safe option
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112 return Val != ID_MMFR0_SHR_IMP_HW_COHERENT;
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117 PopulateLevel2PageTable (
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118 IN UINT32 *SectionEntry,
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119 IN UINT32 PhysicalBase,
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120 IN UINT32 RemainLength,
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121 IN ARM_MEMORY_REGION_ATTRIBUTES Attributes
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127 UINT32 PageAttributes;
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128 UINT32 SectionDescriptor;
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129 UINT32 TranslationTable;
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130 UINT32 BaseSectionAddress;
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131 UINT32 FirstPageOffset;
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133 switch (Attributes) {
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134 case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
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135 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
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136 PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_BACK;
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138 case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE:
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139 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE:
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140 PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_BACK;
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141 PageAttributes &= ~TT_DESCRIPTOR_PAGE_S_SHARED;
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143 case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
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144 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
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145 PageAttributes = TT_DESCRIPTOR_PAGE_WRITE_THROUGH;
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147 case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
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148 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:
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149 PageAttributes = TT_DESCRIPTOR_PAGE_DEVICE;
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151 case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
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152 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
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153 PageAttributes = TT_DESCRIPTOR_PAGE_UNCACHED;
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156 PageAttributes = TT_DESCRIPTOR_PAGE_UNCACHED;
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160 if (PreferNonshareableMemory ()) {
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161 PageAttributes &= ~TT_DESCRIPTOR_PAGE_S_SHARED;
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164 // Check if the Section Entry has already been populated. Otherwise attach a
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165 // Level 2 Translation Table to it
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166 if (*SectionEntry != 0) {
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167 // The entry must be a page table. Otherwise it exists an overlapping in the memory map
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168 if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(*SectionEntry)) {
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169 TranslationTable = *SectionEntry & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK;
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170 } else if ((*SectionEntry & TT_DESCRIPTOR_SECTION_TYPE_MASK) == TT_DESCRIPTOR_SECTION_TYPE_SECTION) {
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171 // Case where a virtual memory map descriptor overlapped a section entry
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173 // Allocate a Level2 Page Table for this Section
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174 TranslationTable = (UINTN)AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_PAGE_SIZE + TRANSLATION_TABLE_PAGE_ALIGNMENT));
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175 TranslationTable = ((UINTN)TranslationTable + TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK;
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177 // Translate the Section Descriptor into Page Descriptor
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178 SectionDescriptor = TT_DESCRIPTOR_PAGE_TYPE_PAGE | ConvertSectionAttributesToPageAttributes (*SectionEntry, FALSE);
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180 BaseSectionAddress = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(*SectionEntry);
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182 // Populate the new Level2 Page Table for the section
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183 PageEntry = (UINT32*)TranslationTable;
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184 for (Index = 0; Index < TRANSLATION_TABLE_PAGE_COUNT; Index++) {
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185 PageEntry[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseSectionAddress + (Index << 12)) | SectionDescriptor;
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188 // Overwrite the section entry to point to the new Level2 Translation Table
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189 *SectionEntry = (TranslationTable & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) |
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190 (IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(Attributes) ? (1 << 3) : 0) |
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191 TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;
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193 // We do not support the other section type (16MB Section)
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198 TranslationTable = (UINTN)AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_PAGE_SIZE + TRANSLATION_TABLE_PAGE_ALIGNMENT));
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199 TranslationTable = ((UINTN)TranslationTable + TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_PAGE_ALIGNMENT_MASK;
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201 ZeroMem ((VOID *)TranslationTable, TRANSLATION_TABLE_PAGE_SIZE);
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203 *SectionEntry = (TranslationTable & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) |
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204 (IS_ARM_MEMORY_REGION_ATTRIBUTES_SECURE(Attributes) ? (1 << 3) : 0) |
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205 TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;
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208 FirstPageOffset = (PhysicalBase & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT;
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209 PageEntry = (UINT32 *)TranslationTable + FirstPageOffset;
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210 Pages = RemainLength / TT_DESCRIPTOR_PAGE_SIZE;
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212 ASSERT (FirstPageOffset + Pages <= TRANSLATION_TABLE_PAGE_COUNT);
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214 for (Index = 0; Index < Pages; Index++) {
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215 *PageEntry++ = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(PhysicalBase) | PageAttributes;
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216 PhysicalBase += TT_DESCRIPTOR_PAGE_SIZE;
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223 FillTranslationTable (
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224 IN UINT32 *TranslationTable,
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225 IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryRegion
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228 UINT32 *SectionEntry;
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230 UINT32 PhysicalBase;
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231 UINT64 RemainLength;
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232 UINT32 PageMapLength;
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234 ASSERT(MemoryRegion->Length > 0);
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236 if (MemoryRegion->PhysicalBase >= SIZE_4GB) {
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240 PhysicalBase = MemoryRegion->PhysicalBase;
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241 RemainLength = MIN(MemoryRegion->Length, SIZE_4GB - PhysicalBase);
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243 switch (MemoryRegion->Attributes) {
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244 case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
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245 Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);
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247 case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE:
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248 Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(0);
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249 Attributes &= ~TT_DESCRIPTOR_SECTION_S_SHARED;
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251 case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
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252 Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(0);
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254 case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
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255 Attributes = TT_DESCRIPTOR_SECTION_DEVICE(0);
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257 case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
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258 Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
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260 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK:
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261 Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);
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263 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK_NONSHAREABLE:
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264 Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK(1);
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265 Attributes &= ~TT_DESCRIPTOR_SECTION_S_SHARED;
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267 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH:
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268 Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH(1);
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270 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_DEVICE:
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271 Attributes = TT_DESCRIPTOR_SECTION_DEVICE(1);
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273 case ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED:
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274 Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(1);
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277 Attributes = TT_DESCRIPTOR_SECTION_UNCACHED(0);
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281 if (PreferNonshareableMemory ()) {
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282 Attributes &= ~TT_DESCRIPTOR_SECTION_S_SHARED;
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285 // Get the first section entry for this mapping
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286 SectionEntry = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
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288 while (RemainLength != 0) {
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289 if (PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE == 0 &&
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290 RemainLength >= TT_DESCRIPTOR_SECTION_SIZE) {
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291 // Case: Physical address aligned on the Section Size (1MB) && the length
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292 // is greater than the Section Size
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293 *SectionEntry++ = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
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294 PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
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295 RemainLength -= TT_DESCRIPTOR_SECTION_SIZE;
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297 PageMapLength = MIN (RemainLength, TT_DESCRIPTOR_SECTION_SIZE -
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298 (PhysicalBase % TT_DESCRIPTOR_SECTION_SIZE));
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300 // Case: Physical address aligned on the Section Size (1MB) && the length
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301 // does not fill a section
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302 // Case: Physical address NOT aligned on the Section Size (1MB)
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303 PopulateLevel2PageTable (SectionEntry++, PhysicalBase, PageMapLength,
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304 MemoryRegion->Attributes);
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306 // If it is the last entry
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307 if (RemainLength < TT_DESCRIPTOR_SECTION_SIZE) {
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311 PhysicalBase += PageMapLength;
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312 RemainLength -= PageMapLength;
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320 IN ARM_MEMORY_REGION_DESCRIPTOR *MemoryTable,
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321 OUT VOID **TranslationTableBase OPTIONAL,
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322 OUT UINTN *TranslationTableSize OPTIONAL
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325 VOID* TranslationTable;
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326 ARM_MEMORY_REGION_ATTRIBUTES TranslationTableAttribute;
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327 UINT32 TTBRAttributes;
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329 // Allocate pages for translation table.
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330 TranslationTable = AllocatePages (EFI_SIZE_TO_PAGES (TRANSLATION_TABLE_SECTION_SIZE + TRANSLATION_TABLE_SECTION_ALIGNMENT));
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331 if (TranslationTable == NULL) {
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332 return RETURN_OUT_OF_RESOURCES;
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334 TranslationTable = (VOID*)(((UINTN)TranslationTable + TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK);
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336 if (TranslationTableBase != NULL) {
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337 *TranslationTableBase = TranslationTable;
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340 if (TranslationTableSize != NULL) {
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341 *TranslationTableSize = TRANSLATION_TABLE_SECTION_SIZE;
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344 ZeroMem (TranslationTable, TRANSLATION_TABLE_SECTION_SIZE);
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346 // By default, mark the translation table as belonging to a uncached region
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347 TranslationTableAttribute = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED;
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348 while (MemoryTable->Length != 0) {
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349 // Find the memory attribute for the Translation Table
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350 if (((UINTN)TranslationTable >= MemoryTable->PhysicalBase) && ((UINTN)TranslationTable <= MemoryTable->PhysicalBase - 1 + MemoryTable->Length)) {
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351 TranslationTableAttribute = MemoryTable->Attributes;
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354 FillTranslationTable (TranslationTable, MemoryTable);
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358 // Translate the Memory Attributes into Translation Table Register Attributes
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359 if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) ||
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360 (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK)) {
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361 TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_WRITE_BACK_ALLOC : TTBR_WRITE_BACK_ALLOC;
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363 // Page tables must reside in memory mapped as write-back cacheable
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365 return RETURN_UNSUPPORTED;
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368 if (TTBRAttributes & TTBR_SHAREABLE) {
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369 if (PreferNonshareableMemory ()) {
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370 TTBRAttributes ^= TTBR_SHAREABLE;
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373 // Unlike the S bit in the short descriptors, which implies inner shareable
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374 // on an implementation that supports two levels, the meaning of the S bit
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375 // in the TTBR depends on the NOS bit, which defaults to Outer Shareable.
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376 // However, we should only set this bit after we have confirmed that the
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377 // implementation supports multiple levels, or else the NOS bit is UNK/SBZP
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379 if (((ArmReadIdMmfr0 () >> 12) & 0xf) != 0) {
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380 TTBRAttributes |= TTBR_NOT_OUTER_SHAREABLE;
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385 ArmCleanInvalidateDataCache ();
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386 ArmInvalidateInstructionCache ();
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388 ArmDisableDataCache ();
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389 ArmDisableInstructionCache();
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390 // TLBs are also invalidated when calling ArmDisableMmu()
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393 // Make sure nothing sneaked into the cache
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394 ArmCleanInvalidateDataCache ();
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395 ArmInvalidateInstructionCache ();
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397 ArmSetTTBR0 ((VOID *)(UINTN)(((UINTN)TranslationTable & ~TRANSLATION_TABLE_SECTION_ALIGNMENT_MASK) | (TTBRAttributes & 0x7F)));
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400 // The TTBCR register value is undefined at reset in the Non-Secure world.
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401 // Writing 0 has the effect of:
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402 // Clearing EAE: Use short descriptors, as mandated by specification.
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403 // Clearing PD0 and PD1: Translation Table Walk Disable is off.
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404 // Clearing N: Perform all translation table walks through TTBR0.
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405 // (0 is the default reset value in systems not implementing
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406 // the Security Extensions.)
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410 ArmSetDomainAccessControl (DOMAIN_ACCESS_CONTROL_NONE(15) |
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411 DOMAIN_ACCESS_CONTROL_NONE(14) |
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412 DOMAIN_ACCESS_CONTROL_NONE(13) |
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413 DOMAIN_ACCESS_CONTROL_NONE(12) |
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414 DOMAIN_ACCESS_CONTROL_NONE(11) |
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415 DOMAIN_ACCESS_CONTROL_NONE(10) |
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416 DOMAIN_ACCESS_CONTROL_NONE( 9) |
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417 DOMAIN_ACCESS_CONTROL_NONE( 8) |
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418 DOMAIN_ACCESS_CONTROL_NONE( 7) |
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419 DOMAIN_ACCESS_CONTROL_NONE( 6) |
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420 DOMAIN_ACCESS_CONTROL_NONE( 5) |
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421 DOMAIN_ACCESS_CONTROL_NONE( 4) |
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422 DOMAIN_ACCESS_CONTROL_NONE( 3) |
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423 DOMAIN_ACCESS_CONTROL_NONE( 2) |
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424 DOMAIN_ACCESS_CONTROL_NONE( 1) |
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425 DOMAIN_ACCESS_CONTROL_CLIENT(0));
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427 ArmEnableInstructionCache();
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428 ArmEnableDataCache();
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430 return RETURN_SUCCESS;
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435 ConvertSectionToPages (
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436 IN EFI_PHYSICAL_ADDRESS BaseAddress
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439 UINT32 FirstLevelIdx;
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440 UINT32 SectionDescriptor;
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441 UINT32 PageTableDescriptor;
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442 UINT32 PageDescriptor;
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445 volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
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446 volatile ARM_PAGE_TABLE_ENTRY *PageTable;
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448 DEBUG ((EFI_D_PAGE, "Converting section at 0x%x to pages\n", (UINTN)BaseAddress));
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450 // Obtain page table base
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451 FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();
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453 // Calculate index into first level translation table for start of modification
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454 FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;
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455 ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);
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457 // Get section attributes and convert to page attributes
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458 SectionDescriptor = FirstLevelTable[FirstLevelIdx];
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459 PageDescriptor = TT_DESCRIPTOR_PAGE_TYPE_PAGE | ConvertSectionAttributesToPageAttributes (SectionDescriptor, FALSE);
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461 // Allocate a page table for the 4KB entries (we use up a full page even though we only need 1KB)
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462 PageTable = (volatile ARM_PAGE_TABLE_ENTRY *)AllocatePages (1);
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463 if (PageTable == NULL) {
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464 return EFI_OUT_OF_RESOURCES;
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467 // Write the page table entries out
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468 for (Index = 0; Index < TRANSLATION_TABLE_PAGE_COUNT; Index++) {
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469 PageTable[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseAddress + (Index << 12)) | PageDescriptor;
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472 // Formulate page table entry, Domain=0, NS=0
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473 PageTableDescriptor = (((UINTN)PageTable) & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) | TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;
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475 // Write the page table entry out, replacing section entry
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476 FirstLevelTable[FirstLevelIdx] = PageTableDescriptor;
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478 return EFI_SUCCESS;
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483 UpdatePageEntries (
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484 IN EFI_PHYSICAL_ADDRESS BaseAddress,
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486 IN UINT64 Attributes,
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487 OUT BOOLEAN *FlushTlbs OPTIONAL
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493 UINT32 FirstLevelIdx;
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495 UINT32 NumPageEntries;
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498 UINT32 PageTableIndex;
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499 UINT32 PageTableEntry;
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500 UINT32 CurrentPageTableEntry;
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503 volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
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504 volatile ARM_PAGE_TABLE_ENTRY *PageTable;
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506 Status = EFI_SUCCESS;
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508 // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)
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509 // EntryValue: values at bit positions specified by EntryMask
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510 EntryMask = TT_DESCRIPTOR_PAGE_TYPE_MASK | TT_DESCRIPTOR_PAGE_AP_MASK;
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511 if (Attributes & EFI_MEMORY_XP) {
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512 EntryValue = TT_DESCRIPTOR_PAGE_TYPE_PAGE_XN;
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514 EntryValue = TT_DESCRIPTOR_PAGE_TYPE_PAGE;
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517 // Although the PI spec is unclear on this, the GCD guarantees that only
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518 // one Attribute bit is set at a time, so the order of the conditionals below
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519 // is irrelevant. If no memory attribute is specified, we preserve whatever
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520 // memory type is set in the page tables, and update the permission attributes
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522 if (Attributes & EFI_MEMORY_UC) {
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523 // modify cacheability attributes
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524 EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;
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525 // map to strongly ordered
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526 EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
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527 } else if (Attributes & EFI_MEMORY_WC) {
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528 // modify cacheability attributes
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529 EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;
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530 // map to normal non-cachable
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531 EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
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532 } else if (Attributes & EFI_MEMORY_WT) {
\r
533 // modify cacheability attributes
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534 EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;
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535 // write through with no-allocate
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536 EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0
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537 } else if (Attributes & EFI_MEMORY_WB) {
\r
538 // modify cacheability attributes
\r
539 EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK;
\r
540 // write back (with allocate)
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541 EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1
\r
542 } else if (Attributes & CACHE_ATTRIBUTE_MASK) {
\r
543 // catch unsupported memory type attributes
\r
545 return EFI_UNSUPPORTED;
\r
548 if (Attributes & EFI_MEMORY_RO) {
\r
549 EntryValue |= TT_DESCRIPTOR_PAGE_AP_RO_RO;
\r
551 EntryValue |= TT_DESCRIPTOR_PAGE_AP_RW_RW;
\r
554 // Obtain page table base
\r
555 FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();
\r
557 // Calculate number of 4KB page table entries to change
\r
558 NumPageEntries = Length / TT_DESCRIPTOR_PAGE_SIZE;
\r
560 // Iterate for the number of 4KB pages to change
\r
562 for(p = 0; p < NumPageEntries; p++) {
\r
563 // Calculate index into first level translation table for page table value
\r
565 FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress + Offset) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;
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566 ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);
\r
568 // Read the descriptor from the first level page table
\r
569 Descriptor = FirstLevelTable[FirstLevelIdx];
\r
571 // Does this descriptor need to be converted from section entry to 4K pages?
\r
572 if (!TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(Descriptor)) {
\r
573 Status = ConvertSectionToPages (FirstLevelIdx << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
\r
574 if (EFI_ERROR(Status)) {
\r
579 // Re-read descriptor
\r
580 Descriptor = FirstLevelTable[FirstLevelIdx];
\r
581 if (FlushTlbs != NULL) {
\r
586 // Obtain page table base address
\r
587 PageTable = (ARM_PAGE_TABLE_ENTRY *)TT_DESCRIPTOR_PAGE_BASE_ADDRESS(Descriptor);
\r
589 // Calculate index into the page table
\r
590 PageTableIndex = ((BaseAddress + Offset) & TT_DESCRIPTOR_PAGE_INDEX_MASK) >> TT_DESCRIPTOR_PAGE_BASE_SHIFT;
\r
591 ASSERT (PageTableIndex < TRANSLATION_TABLE_PAGE_COUNT);
\r
594 CurrentPageTableEntry = PageTable[PageTableIndex];
\r
596 // Mask off appropriate fields
\r
597 PageTableEntry = CurrentPageTableEntry & ~EntryMask;
\r
599 // Mask in new attributes and/or permissions
\r
600 PageTableEntry |= EntryValue;
\r
602 if (CurrentPageTableEntry != PageTableEntry) {
\r
603 Mva = (VOID *)(UINTN)((((UINTN)FirstLevelIdx) << TT_DESCRIPTOR_SECTION_BASE_SHIFT) + (PageTableIndex << TT_DESCRIPTOR_PAGE_BASE_SHIFT));
\r
605 // Only need to update if we are changing the entry
\r
606 PageTable[PageTableIndex] = PageTableEntry;
\r
607 ArmUpdateTranslationTableEntry ((VOID *)&PageTable[PageTableIndex], Mva);
\r
610 Status = EFI_SUCCESS;
\r
611 Offset += TT_DESCRIPTOR_PAGE_SIZE;
\r
613 } // End first level translation table loop
\r
620 UpdateSectionEntries (
\r
621 IN EFI_PHYSICAL_ADDRESS BaseAddress,
\r
623 IN UINT64 Attributes
\r
626 EFI_STATUS Status = EFI_SUCCESS;
\r
629 UINT32 FirstLevelIdx;
\r
630 UINT32 NumSections;
\r
632 UINT32 CurrentDescriptor;
\r
635 volatile ARM_FIRST_LEVEL_DESCRIPTOR *FirstLevelTable;
\r
637 // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone)
\r
638 // EntryValue: values at bit positions specified by EntryMask
\r
640 // Make sure we handle a section range that is unmapped
\r
641 EntryMask = TT_DESCRIPTOR_SECTION_TYPE_MASK | TT_DESCRIPTOR_SECTION_XN_MASK |
\r
642 TT_DESCRIPTOR_SECTION_AP_MASK;
\r
643 EntryValue = TT_DESCRIPTOR_SECTION_TYPE_SECTION;
\r
645 // Although the PI spec is unclear on this, the GCD guarantees that only
\r
646 // one Attribute bit is set at a time, so the order of the conditionals below
\r
647 // is irrelevant. If no memory attribute is specified, we preserve whatever
\r
648 // memory type is set in the page tables, and update the permission attributes
\r
650 if (Attributes & EFI_MEMORY_UC) {
\r
651 // modify cacheability attributes
\r
652 EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;
\r
653 // map to strongly ordered
\r
654 EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0
\r
655 } else if (Attributes & EFI_MEMORY_WC) {
\r
656 // modify cacheability attributes
\r
657 EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;
\r
658 // map to normal non-cachable
\r
659 EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0
\r
660 } else if (Attributes & EFI_MEMORY_WT) {
\r
661 // modify cacheability attributes
\r
662 EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;
\r
663 // write through with no-allocate
\r
664 EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0
\r
665 } else if (Attributes & EFI_MEMORY_WB) {
\r
666 // modify cacheability attributes
\r
667 EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK;
\r
668 // write back (with allocate)
\r
669 EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1
\r
670 } else if (Attributes & CACHE_ATTRIBUTE_MASK) {
\r
671 // catch unsupported memory type attributes
\r
673 return EFI_UNSUPPORTED;
\r
676 if (Attributes & EFI_MEMORY_RO) {
\r
677 EntryValue |= TT_DESCRIPTOR_SECTION_AP_RO_RO;
\r
679 EntryValue |= TT_DESCRIPTOR_SECTION_AP_RW_RW;
\r
682 if (Attributes & EFI_MEMORY_XP) {
\r
683 EntryValue |= TT_DESCRIPTOR_SECTION_XN_MASK;
\r
686 // obtain page table base
\r
687 FirstLevelTable = (ARM_FIRST_LEVEL_DESCRIPTOR *)ArmGetTTBR0BaseAddress ();
\r
689 // calculate index into first level translation table for start of modification
\r
690 FirstLevelIdx = TT_DESCRIPTOR_SECTION_BASE_ADDRESS(BaseAddress) >> TT_DESCRIPTOR_SECTION_BASE_SHIFT;
\r
691 ASSERT (FirstLevelIdx < TRANSLATION_TABLE_SECTION_COUNT);
\r
693 // calculate number of 1MB first level entries this applies to
\r
694 NumSections = Length / TT_DESCRIPTOR_SECTION_SIZE;
\r
696 // iterate through each descriptor
\r
697 for(i=0; i<NumSections; i++) {
\r
698 CurrentDescriptor = FirstLevelTable[FirstLevelIdx + i];
\r
700 // has this descriptor already been coverted to pages?
\r
701 if (TT_DESCRIPTOR_SECTION_TYPE_IS_PAGE_TABLE(CurrentDescriptor)) {
\r
702 // forward this 1MB range to page table function instead
\r
703 Status = UpdatePageEntries (
\r
704 (FirstLevelIdx + i) << TT_DESCRIPTOR_SECTION_BASE_SHIFT,
\r
705 TT_DESCRIPTOR_SECTION_SIZE,
\r
709 // still a section entry
\r
711 if (CurrentDescriptor != 0) {
\r
712 // mask off appropriate fields
\r
713 Descriptor = CurrentDescriptor & ~EntryMask;
\r
715 Descriptor = ((UINTN)FirstLevelIdx + i) << TT_DESCRIPTOR_SECTION_BASE_SHIFT;
\r
718 // mask in new attributes and/or permissions
\r
719 Descriptor |= EntryValue;
\r
721 if (CurrentDescriptor != Descriptor) {
\r
722 Mva = (VOID *)(UINTN)(((UINTN)FirstLevelIdx + i) << TT_DESCRIPTOR_SECTION_BASE_SHIFT);
\r
724 // Only need to update if we are changing the descriptor
\r
725 FirstLevelTable[FirstLevelIdx + i] = Descriptor;
\r
726 ArmUpdateTranslationTableEntry ((VOID *)&FirstLevelTable[FirstLevelIdx + i], Mva);
\r
729 Status = EFI_SUCCESS;
\r
737 ArmSetMemoryAttributes (
\r
738 IN EFI_PHYSICAL_ADDRESS BaseAddress,
\r
740 IN UINT64 Attributes
\r
744 UINT64 ChunkLength;
\r
748 return EFI_SUCCESS;
\r
752 while (Length > 0) {
\r
753 if ((BaseAddress % TT_DESCRIPTOR_SECTION_SIZE == 0) &&
\r
754 Length >= TT_DESCRIPTOR_SECTION_SIZE) {
\r
756 ChunkLength = Length - Length % TT_DESCRIPTOR_SECTION_SIZE;
\r
758 DEBUG ((DEBUG_PAGE,
\r
759 "SetMemoryAttributes(): MMU section 0x%lx length 0x%lx to %lx\n",
\r
760 BaseAddress, ChunkLength, Attributes));
\r
762 Status = UpdateSectionEntries (BaseAddress, ChunkLength, Attributes);
\r
768 // Process page by page until the next section boundary, but only if
\r
769 // we have more than a section's worth of area to deal with after that.
\r
771 ChunkLength = TT_DESCRIPTOR_SECTION_SIZE -
\r
772 (BaseAddress % TT_DESCRIPTOR_SECTION_SIZE);
\r
773 if (ChunkLength + TT_DESCRIPTOR_SECTION_SIZE > Length) {
\r
774 ChunkLength = Length;
\r
777 DEBUG ((DEBUG_PAGE,
\r
778 "SetMemoryAttributes(): MMU page 0x%lx length 0x%lx to %lx\n",
\r
779 BaseAddress, ChunkLength, Attributes));
\r
781 Status = UpdatePageEntries (BaseAddress, ChunkLength, Attributes,
\r
785 if (EFI_ERROR (Status)) {
\r
789 BaseAddress += ChunkLength;
\r
790 Length -= ChunkLength;
\r
794 ArmInvalidateTlb ();
\r
800 ArmSetMemoryRegionNoExec (
\r
801 IN EFI_PHYSICAL_ADDRESS BaseAddress,
\r
805 return ArmSetMemoryAttributes (BaseAddress, Length, EFI_MEMORY_XP);
\r
809 ArmClearMemoryRegionNoExec (
\r
810 IN EFI_PHYSICAL_ADDRESS BaseAddress,
\r
814 return ArmSetMemoryAttributes (BaseAddress, Length, __EFI_MEMORY_RWX);
\r
818 ArmSetMemoryRegionReadOnly (
\r
819 IN EFI_PHYSICAL_ADDRESS BaseAddress,
\r
823 return ArmSetMemoryAttributes (BaseAddress, Length, EFI_MEMORY_RO);
\r
827 ArmClearMemoryRegionReadOnly (
\r
828 IN EFI_PHYSICAL_ADDRESS BaseAddress,
\r
832 return ArmSetMemoryAttributes (BaseAddress, Length, __EFI_MEMORY_RWX);
\r
837 ArmMmuBaseLibConstructor (
\r
841 return RETURN_SUCCESS;
\r