ArmPkg/Library/BaseMemoryLibVstm/Arm/SetMem.asm

   1 ;------------------------------------------------------------------------------
   2 ;
   3 ; SetMem() worker for ARM
   4 ;
   5 ; This file started out as C code that did 64 bit moves if the buffer was
   6 ; 32-bit aligned, else it does a byte copy. It also does a byte copy for
   7 ; any trailing bytes. Update to use VSTM/VLDM to do 128 byte writes.
   8 ;
   9 ; Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
  10 ; This program and the accompanying materials
  11 ; are licensed and made available under the terms and conditions of the BSD License
  12 ; which accompanies this distribution.  The full text of the license may be found at
  13 ; http://opensource.org/licenses/bsd-license.php
  14 ;
  15 ; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  16 ; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  17 ;
  18
  19 /**
  20   Set Buffer to Value for Size bytes.
  21
  22   @param  Buffer   Memory to set.
  23   @param  Length   Number of bytes to set
  24   @param  Value    Value of the set operation.
  25
  26   @return Buffer
  27
  28 VOID *
  29 EFIAPI
  30 InternalMemSetMem (
  31   OUT     VOID                      *Buffer,
  32   IN      UINTN                     Length,
  33   IN      UINT8                     Value
  34   )
  35 **/
  36 \s\s
  37 \s\sEXPORT InternalMemSetMem
  38 \s\s
  39 \s\sAREA AsmMemStuff, CODE, READONLY
  40
  41 InternalMemSetMem
  42 \s\sstmfd\s\ssp!, {lr}
  43 \s\stst\s\s  r0, #3
  44 \s\smovne\s\sr3, #0
  45 \s\smoveq\s\sr3, #1
  46 \s\scmp\s\s  r1, #127
  47 \s\smovls lr, #0
  48 \s\sandhi\s\slr, r3, #1
  49 \s\scmp\s\s  lr, #0
  50 \s\smov\s\s  r12, r0
  51 \s\sbne\s\s  L31
  52 L32
  53 \s\smov\s\s  r3, #0
  54 \s\sb\s\s    L43
  55 L31
  56   vdup.8  q0,r2
  57   vmov    q1,q0
  58   vmov    q2,q0
  59   vmov    q3,q0
  60   vmov    q4,q0
  61   vmov    q5,q0
  62   vmov    q6,q0
  63   vmov    q7,q0
  64 \s\sb\s\s      L32
  65 L34
  66 \s\scmp\s\s    lr, #0
  67 \s\sstreqb\s\sr2, [r12], #1
  68 \s\ssubeq\s\s  r1, r1, #1
  69 \s\sbeq\s\s    L43
  70 \s\ssub\s\s    r1, r1, #128
  71 \s\scmp\s\s    r1, #127
  72 \s\smovls\s\s  lr, r3
  73 \s\svstm    r12!, {d0-d15}
  74 L43
  75 \s\scmp\s\s    r1, #0
  76 \s\sbne\s\s    L34
  77 \s\sldmfd\s\s  sp!, {pc}
  78 \s\s
  79   END
  80