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1 #------------------------------------------------------------------------------
2 #
3 # Copyright (c) 2011, ARM. All rights reserved.<BR>
4 #
5 # SPDX-License-Identifier: BSD-2-Clause-Patent
6 #
7 #------------------------------------------------------------------------------
8
9 .text
10 .align 2
11 GCC_ASM_EXPORT(__aeabi_uidiv)
12 GCC_ASM_EXPORT(__aeabi_uidivmod)
13 GCC_ASM_EXPORT(__aeabi_idiv)
14 GCC_ASM_EXPORT(__aeabi_idivmod)
15
16 # AREA Math, CODE, READONLY
17
18 #
19 #UINT32
20 #EFIAPI
21 #__aeabi_uidivmode (
22 # IN UINT32 Dividen
23 # IN UINT32 Divisor
24 # );
25 #
26
27 ASM_PFX(__aeabi_uidiv):
28 ASM_PFX(__aeabi_uidivmod):
29 rsbs r12, r1, r0, LSR #4
30 mov r2, #0
31 bcc ASM_PFX(__arm_div4)
32 rsbs r12, r1, r0, LSR #8
33 bcc ASM_PFX(__arm_div8)
34 mov r3, #0
35 b ASM_PFX(__arm_div_large)
36
37 #
38 #INT32
39 #EFIAPI
40 #__aeabi_idivmode (
41 # IN INT32 Dividen
42 # IN INT32 Divisor
43 # );
44 #
45 ASM_PFX(__aeabi_idiv):
46 ASM_PFX(__aeabi_idivmod):
47 orrs r12, r0, r1
48 bmi ASM_PFX(__arm_div_negative)
49 rsbs r12, r1, r0, LSR #1
50 mov r2, #0
51 bcc ASM_PFX(__arm_div1)
52 rsbs r12, r1, r0, LSR #4
53 bcc ASM_PFX(__arm_div4)
54 rsbs r12, r1, r0, LSR #8
55 bcc ASM_PFX(__arm_div8)
56 mov r3, #0
57 b ASM_PFX(__arm_div_large)
58 ASM_PFX(__arm_div8):
59 rsbs r12, r1, r0, LSR #7
60 subcs r0, r0, r1, LSL #7
61 adc r2, r2, r2
62 rsbs r12, r1, r0,LSR #6
63 subcs r0, r0, r1, LSL #6
64 adc r2, r2, r2
65 rsbs r12, r1, r0, LSR #5
66 subcs r0, r0, r1, LSL #5
67 adc r2, r2, r2
68 rsbs r12, r1, r0, LSR #4
69 subcs r0, r0, r1, LSL #4
70 adc r2, r2, r2
71 ASM_PFX(__arm_div4):
72 rsbs r12, r1, r0, LSR #3
73 subcs r0, r0, r1, LSL #3
74 adc r2, r2, r2
75 rsbs r12, r1, r0, LSR #2
76 subcs r0, r0, r1, LSL #2
77 adcs r2, r2, r2
78 rsbs r12, r1, r0, LSR #1
79 subcs r0, r0, r1, LSL #1
80 adc r2, r2, r2
81 ASM_PFX(__arm_div1):
82 subs r1, r0, r1
83 movcc r1, r0
84 adc r0, r2, r2
85 bx r14
86 ASM_PFX(__arm_div_negative):
87 ands r2, r1, #0x80000000
88 rsbmi r1, r1, #0
89 eors r3, r2, r0, ASR #32
90 rsbcs r0, r0, #0
91 rsbs r12, r1, r0, LSR #4
92 bcc label1
93 rsbs r12, r1, r0, LSR #8
94 bcc label2
95 ASM_PFX(__arm_div_large):
96 lsl r1, r1, #6
97 rsbs r12, r1, r0, LSR #8
98 orr r2, r2, #0xfc000000
99 bcc label2
100 lsl r1, r1, #6
101 rsbs r12, r1, r0, LSR #8
102 orr r2, r2, #0x3f00000
103 bcc label2
104 lsl r1, r1, #6
105 rsbs r12, r1, r0, LSR #8
106 orr r2, r2, #0xfc000
107 orrcs r2, r2, #0x3f00
108 lslcs r1, r1, #6
109 rsbs r12, r1, #0
110 bcs ASM_PFX(__aeabi_idiv0)
111 label3:
112 lsrcs r1, r1, #6
113 label2:
114 rsbs r12, r1, r0, LSR #7
115 subcs r0, r0, r1, LSL #7
116 adc r2, r2, r2
117 rsbs r12, r1, r0, LSR #6
118 subcs r0, r0, r1, LSL #6
119 adc r2, r2, r2
120 rsbs r12, r1, r0, LSR #5
121 subcs r0, r0, r1, LSL #5
122 adc r2, r2, r2
123 rsbs r12, r1, r0, LSR #4
124 subcs r0, r0, r1, LSL #4
125 adc r2, r2, r2
126 label1:
127 rsbs r12, r1, r0, LSR #3
128 subcs r0, r0, r1, LSL #3
129 adc r2, r2, r2
130 rsbs r12, r1, r0, LSR #2
131 subcs r0, r0, r1, LSL #2
132 adcs r2, r2, r2
133 bcs label3
134 rsbs r12, r1, r0, LSR #1
135 subcs r0, r0, r1, LSL #1
136 adc r2, r2, r2
137 subs r1, r0, r1
138 movcc r1, r0
139 adc r0, r2, r2
140 asrs r3, r3, #31
141 rsbmi r0, r0, #0
142 rsbcs r1, r1, #0
143 bx r14
144
145 @ What to do about division by zero? For now, just return.
146 ASM_PFX(__aeabi_idiv0):
147 bx r14