ArmPkg/Library/CompilerIntrinsicsLib/Arm/div.asm

   1 //------------------------------------------------------------------------------
   2 //
   3 // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4 //
   5 // This program and the accompanying materials
   6 // are licensed and made available under the terms and conditions of the BSD License
   7 // which accompanies this distribution.  The full text of the license may be found at
   8 // http://opensource.org/licenses/bsd-license.php
   9 //
  10 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 //
  13 //------------------------------------------------------------------------------
  14
  15
  16     EXPORT  __aeabi_uidiv
  17     EXPORT  __aeabi_uidivmod
  18     EXPORT  __aeabi_idiv
  19     EXPORT  __aeabi_idivmod
  20
  21     AREA  Math, CODE, READONLY
  22
  23 ;
  24 ;UINT32
  25 ;EFIAPI
  26 ;__aeabi_uidivmode (
  27 ;  IN UINT32  Dividen
  28 ;  IN UINT32  Divisor
  29 ;  );
  30 ;
  31
  32 __aeabi_uidiv
  33 __aeabi_uidivmod
  34     RSBS    r12, r1, r0, LSR #4
  35     MOV     r2, #0
  36     BCC     __arm_div4
  37     RSBS    r12, r1, r0, LSR #8
  38     BCC     __arm_div8
  39     MOV     r3, #0
  40     B       __arm_div_large
  41
  42 ;
  43 ;INT32
  44 ;EFIAPI
  45 ;__aeabi_idivmode (
  46 ;  IN INT32  Dividen
  47 ;  IN INT32  Divisor
  48 ;  );
  49 ;
  50 __aeabi_idiv
  51 __aeabi_idivmod
  52     ORRS    r12, r0, r1
  53     BMI     __arm_div_negative
  54     RSBS    r12, r1, r0, LSR #1
  55     MOV     r2, #0
  56     BCC     __arm_div1
  57     RSBS    r12, r1, r0, LSR #4
  58     BCC     __arm_div4
  59     RSBS    r12, r1, r0, LSR #8
  60     BCC     __arm_div8
  61     MOV     r3, #0
  62     B       __arm_div_large
  63 __arm_div8
  64     RSBS    r12, r1, r0, LSR #7
  65     SUBCS   r0, r0, r1, LSL #7
  66     ADC     r2, r2, r2
  67     RSBS    r12, r1, r0,LSR #6
  68     SUBCS   r0, r0, r1, LSL #6
  69     ADC     r2, r2, r2
  70     RSBS    r12, r1, r0, LSR #5
  71     SUBCS   r0, r0, r1, LSL #5
  72     ADC     r2, r2, r2
  73     RSBS    r12, r1, r0, LSR #4
  74     SUBCS   r0, r0, r1, LSL #4
  75     ADC     r2, r2, r2
  76 __arm_div4
  77     RSBS    r12, r1, r0, LSR #3
  78     SUBCS   r0, r0, r1, LSL #3
  79     ADC     r2, r2, r2
  80     RSBS    r12, r1, r0, LSR #2
  81     SUBCS   r0, r0, r1, LSL #2
  82     ADCS    r2, r2, r2
  83     RSBS    r12, r1, r0, LSR #1
  84     SUBCS   r0, r0, r1, LSL #1
  85     ADC     r2, r2, r2
  86 __arm_div1
  87     SUBS    r1, r0, r1
  88     MOVCC   r1, r0
  89     ADC     r0, r2, r2
  90     BX      r14
  91 __arm_div_negative
  92     ANDS    r2, r1, #0x80000000
  93     RSBMI   r1, r1, #0
  94     EORS    r3, r2, r0, ASR #32
  95     RSBCS   r0, r0, #0
  96     RSBS    r12, r1, r0, LSR #4
  97     BCC     label1
  98     RSBS    r12, r1, r0, LSR #8
  99     BCC     label2
 100 __arm_div_large
 101     LSL     r1, r1, #6
 102     RSBS    r12, r1, r0, LSR #8
 103     ORR     r2, r2, #0xfc000000
 104     BCC     label2
 105     LSL     r1, r1, #6
 106     RSBS    r12, r1, r0, LSR #8
 107     ORR     r2, r2, #0x3f00000
 108     BCC     label2
 109     LSL     r1, r1, #6
 110     RSBS    r12, r1, r0, LSR #8
 111     ORR     r2, r2, #0xfc000
 112     ORRCS   r2, r2, #0x3f00
 113     LSLCS   r1, r1, #6
 114     RSBS    r12, r1, #0
 115     BCS     __aeabi_idiv0
 116 label3
 117     LSRCS   r1, r1, #6
 118 label2
 119     RSBS    r12, r1, r0, LSR #7
 120     SUBCS   r0, r0, r1, LSL #7
 121     ADC     r2, r2, r2
 122     RSBS    r12, r1, r0, LSR #6
 123     SUBCS   r0, r0, r1, LSL #6
 124     ADC     r2, r2, r2
 125     RSBS    r12, r1, r0, LSR #5
 126     SUBCS   r0, r0, r1, LSL #5
 127     ADC     r2, r2, r2
 128     RSBS    r12, r1, r0, LSR #4
 129     SUBCS   r0, r0, r1, LSL #4
 130     ADC     r2, r2, r2
 131 label1
 132     RSBS    r12, r1, r0, LSR #3
 133     SUBCS   r0, r0, r1, LSL #3
 134     ADC     r2, r2, r2
 135     RSBS    r12, r1, r0, LSR #2
 136     SUBCS   r0, r0, r1, LSL #2
 137     ADCS    r2, r2, r2
 138     BCS     label3
 139     RSBS    r12, r1, r0, LSR #1
 140     SUBCS   r0, r0, r1, LSL #1
 141     ADC     r2, r2, r2
 142     SUBS    r1, r0, r1
 143     MOVCC   r1, r0
 144     ADC     r0, r2, r2
 145     ASRS    r3, r3, #31
 146     RSBMI   r0, r0, #0
 147     RSBCS   r1, r1, #0
 148     BX      r14
 149
 150     ; What to do about division by zero?  For now, just return.
 151 __aeabi_idiv0
 152     BX      r14
 153
 154     END
 155