ArmPkg/Library/CompilerIntrinsicsLib/Arm/div.asm

   1 //------------------------------------------------------------------------------
   2 //
   3 // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
   4 // Copyright (c) 2018, Pete Batard. All rights reserved.<BR>
   5 //
   6 // SPDX-License-Identifier: BSD-2-Clause-Patent
   7 //
   8 //------------------------------------------------------------------------------
   9
  10
  11     EXPORT  __aeabi_uidiv
  12     EXPORT  __aeabi_uidivmod
  13     EXPORT  __aeabi_idiv
  14     EXPORT  __aeabi_idivmod
  15     EXPORT  __rt_udiv
  16     EXPORT  __rt_sdiv
  17
  18     AREA  Math, CODE, READONLY
  19
  20 ;
  21 ;UINT32
  22 ;EFIAPI
  23 ;__aeabi_uidivmod (
  24 ;  IN UINT32  Dividend
  25 ;  IN UINT32  Divisor
  26 ;  );
  27 ;
  28 __aeabi_uidiv
  29 __aeabi_uidivmod
  30     RSBS    r12, r1, r0, LSR #4
  31     MOV     r2, #0
  32     BCC     __arm_div4
  33     RSBS    r12, r1, r0, LSR #8
  34     BCC     __arm_div8
  35     MOV     r3, #0
  36     B       __arm_div_large
  37
  38 ;
  39 ;UINT64
  40 ;EFIAPI
  41 ;__rt_udiv (
  42 ;  IN UINT32  Divisor,
  43 ;  IN UINT32  Dividend
  44 ;  );
  45 ;
  46 __rt_udiv
  47     ; Swap R0 and R1
  48     MOV     r12, r0
  49     MOV     r0, r1
  50     MOV     r1, r12
  51     B       __aeabi_uidivmod
  52
  53 ;
  54 ;UINT64
  55 ;EFIAPI
  56 ;__rt_sdiv (
  57 ;  IN INT32  Divisor,
  58 ;  IN INT32  Dividend
  59 ;  );
  60 ;
  61 __rt_sdiv
  62     ; Swap R0 and R1
  63     MOV     r12, r0
  64     MOV     r0, r1
  65     MOV     r1, r12
  66     B       __aeabi_idivmod
  67
  68 ;
  69 ;INT32
  70 ;EFIAPI
  71 ;__aeabi_idivmod (
  72 ;  IN INT32  Dividend
  73 ;  IN INT32  Divisor
  74 ;  );
  75 ;
  76 __aeabi_idiv
  77 __aeabi_idivmod
  78     ORRS    r12, r0, r1
  79     BMI     __arm_div_negative
  80     RSBS    r12, r1, r0, LSR #1
  81     MOV     r2, #0
  82     BCC     __arm_div1
  83     RSBS    r12, r1, r0, LSR #4
  84     BCC     __arm_div4
  85     RSBS    r12, r1, r0, LSR #8
  86     BCC     __arm_div8
  87     MOV     r3, #0
  88     B       __arm_div_large
  89 __arm_div8
  90     RSBS    r12, r1, r0, LSR #7
  91     SUBCS   r0, r0, r1, LSL #7
  92     ADC     r2, r2, r2
  93     RSBS    r12, r1, r0,LSR #6
  94     SUBCS   r0, r0, r1, LSL #6
  95     ADC     r2, r2, r2
  96     RSBS    r12, r1, r0, LSR #5
  97     SUBCS   r0, r0, r1, LSL #5
  98     ADC     r2, r2, r2
  99     RSBS    r12, r1, r0, LSR #4
 100     SUBCS   r0, r0, r1, LSL #4
 101     ADC     r2, r2, r2
 102 __arm_div4
 103     RSBS    r12, r1, r0, LSR #3
 104     SUBCS   r0, r0, r1, LSL #3
 105     ADC     r2, r2, r2
 106     RSBS    r12, r1, r0, LSR #2
 107     SUBCS   r0, r0, r1, LSL #2
 108     ADCS    r2, r2, r2
 109     RSBS    r12, r1, r0, LSR #1
 110     SUBCS   r0, r0, r1, LSL #1
 111     ADC     r2, r2, r2
 112 __arm_div1
 113     SUBS    r1, r0, r1
 114     MOVCC   r1, r0
 115     ADC     r0, r2, r2
 116     BX      r14
 117 __arm_div_negative
 118     ANDS    r2, r1, #0x80000000
 119     RSBMI   r1, r1, #0
 120     EORS    r3, r2, r0, ASR #32
 121     RSBCS   r0, r0, #0
 122     RSBS    r12, r1, r0, LSR #4
 123     BCC     label1
 124     RSBS    r12, r1, r0, LSR #8
 125     BCC     label2
 126 __arm_div_large
 127     LSL     r1, r1, #6
 128     RSBS    r12, r1, r0, LSR #8
 129     ORR     r2, r2, #0xfc000000
 130     BCC     label2
 131     LSL     r1, r1, #6
 132     RSBS    r12, r1, r0, LSR #8
 133     ORR     r2, r2, #0x3f00000
 134     BCC     label2
 135     LSL     r1, r1, #6
 136     RSBS    r12, r1, r0, LSR #8
 137     ORR     r2, r2, #0xfc000
 138     ORRCS   r2, r2, #0x3f00
 139     LSLCS   r1, r1, #6
 140     RSBS    r12, r1, #0
 141     BCS     __aeabi_idiv0
 142 label3
 143     LSRCS   r1, r1, #6
 144 label2
 145     RSBS    r12, r1, r0, LSR #7
 146     SUBCS   r0, r0, r1, LSL #7
 147     ADC     r2, r2, r2
 148     RSBS    r12, r1, r0, LSR #6
 149     SUBCS   r0, r0, r1, LSL #6
 150     ADC     r2, r2, r2
 151     RSBS    r12, r1, r0, LSR #5
 152     SUBCS   r0, r0, r1, LSL #5
 153     ADC     r2, r2, r2
 154     RSBS    r12, r1, r0, LSR #4
 155     SUBCS   r0, r0, r1, LSL #4
 156     ADC     r2, r2, r2
 157 label1
 158     RSBS    r12, r1, r0, LSR #3
 159     SUBCS   r0, r0, r1, LSL #3
 160     ADC     r2, r2, r2
 161     RSBS    r12, r1, r0, LSR #2
 162     SUBCS   r0, r0, r1, LSL #2
 163     ADCS    r2, r2, r2
 164     BCS     label3
 165     RSBS    r12, r1, r0, LSR #1
 166     SUBCS   r0, r0, r1, LSL #1
 167     ADC     r2, r2, r2
 168     SUBS    r1, r0, r1
 169     MOVCC   r1, r0
 170     ADC     r0, r2, r2
 171     ASRS    r3, r3, #31
 172     RSBMI   r0, r0, #0
 173     RSBCS   r1, r1, #0
 174     BX      r14
 175
 176     ; What to do about division by zero?  For now, just return.
 177 __aeabi_idiv0
 178     BX      r14
 179
 180     END