44597cefd83e7e98ffd8ae90eca48056a603ca61
[mirror_edk2.git] / ArmPlatformPkg / ArmPlatformPkg.dec
1 #/** @file
2 #
3 # Copyright (c) 2011-2015, ARM Limited. All rights reserved.
4 #
5 # This program and the accompanying materials
6 # are licensed and made available under the terms and conditions of the BSD License
7 # which accompanies this distribution. The full text of the license may be found at
8 # http://opensource.org/licenses/bsd-license.php
9 #
10 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12 #
13 #**/
14
15 [Defines]
16 DEC_SPECIFICATION = 0x00010005
17 PACKAGE_NAME = ArmPlatformPkg
18 PACKAGE_GUID = 3308e0a0-1d94-11e0-915c-0002a5d5c51b
19 PACKAGE_VERSION = 0.1
20
21 ################################################################################
22 #
23 # Include Section - list of Include Paths that are provided by this package.
24 # Comments are used for Keywords and Module Types.
25 #
26 # Supported Module Types:
27 # BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
28 #
29 ################################################################################
30 [Includes.common]
31 Include # Root include for the package
32
33 [Guids.common]
34 gArmPlatformTokenSpaceGuid = { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }
35 #
36 # Following Guid must match FILE_GUID in MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
37 #
38 gVariableRuntimeDxeFileGuid = { 0xcbd2e4d5, 0x7068, 0x4ff5, { 0xb4, 0x62, 0x98, 0x22, 0xb4, 0xad, 0x8d, 0x60 } }
39
40 ## Include/Guid/ArmGlobalVariableHob.h
41 gArmGlobalVariableGuid = { 0xc3253c90, 0xa24f, 0x4599, { 0xa6, 0x64, 0x1f, 0x88, 0x13, 0x77, 0x8f, 0xc9} }
42
43 gArmBootMonFsFileInfoGuid = { 0x41e26b9c, 0xada6, 0x45b3, { 0x80, 0x8e, 0x23, 0x57, 0xa3, 0x5b, 0x60, 0xd6 } }
44
45 [Ppis]
46 ## Include/Ppi/ArmGlobalVariable.h
47 gArmGlobalVariablePpiGuid = { 0xab1c1816, 0xd542, 0x4e6f, {0x9b, 0x1e, 0x8e, 0xcd, 0x92, 0x53, 0xe2, 0xe7} }
48
49 [PcdsFeatureFlag.common]
50 # Set this PCD to TRUE to map NORFlash at 0x0. FALSE means the DRAM is mapped at 0x0.
51 gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping|FALSE|BOOLEAN|0x00000012
52
53 gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE|BOOLEAN|0x00000001
54 gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|FALSE|BOOLEAN|0x00000002
55 gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004
56
57 gArmPlatformTokenSpaceGuid.PcdNorFlashCheckBlockLocked|FALSE|BOOLEAN|0x0000003C
58
59 # Disable the GOP controller on ExitBootServices(). By default the value is FALSE,
60 # we assume the OS will handle the FrameBuffer from the UEFI GOP information.
61 gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices|FALSE|BOOLEAN|0x0000003D
62
63 [PcdsFixedAtBuild.common]
64 gArmPlatformTokenSpaceGuid.PcdCoreCount|1|UINT32|0x00000039
65 gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038
66
67 # Stack for CPU Cores in Secure Mode
68 gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT32|0x00000005
69 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000|UINT32|0x00000036
70 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000|UINT32|0x00000006
71
72 # Stack for CPU Cores in Non Secure Mode
73 gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT64|0x00000009
74 gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000|UINT32|0x00000037
75 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000|UINT32|0x0000000A
76
77 # Size of the region used by UEFI in permanent memory (Reserved 128MB by default)
78 gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000|UINT32|0x00000015
79
80 # Size to reserve in the primary core stack for PEI Global Variables
81 # = sizeof(UINTN) /* PcdPeiServicePtr or HobListPtr */
82 gArmPlatformTokenSpaceGuid.PcdPeiGlobalVariableSize|0x4|UINT32|0x00000016
83 # PeiServicePtr and HobListPtr shares the same location in the PEI Global Variable list
84 # PeiServicePtr is only valid with PEI Core and HobListPtr only when the PEI Core is skipped.
85 gArmPlatformTokenSpaceGuid.PcdPeiServicePtrGlobalOffset|0x0|UINT32|0x00000017
86 gArmPlatformTokenSpaceGuid.PcdHobListPtrGlobalOffset|0x0|UINT32|0x00000018
87
88 # Size to reserve in the primary core stack for SEC Global Variables
89 gArmPlatformTokenSpaceGuid.PcdSecGlobalVariableSize|0x0|UINT32|0x00000031
90
91 # Boot Monitor FileSystem
92 gArmPlatformTokenSpaceGuid.PcdBootMonFsSupportedDevicePaths|L""|VOID*|0x0000003A
93
94 #
95 # ARM Primecells
96 #
97
98 ## SP804 DualTimer
99 gArmPlatformTokenSpaceGuid.PcdSP804TimerFrequencyInMHz|1|UINT32|0x0000001D
100 gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|0|UINT32|0x0000001E
101 gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0|UINT32|0x0000002A
102 gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0|UINT32|0x0000002B
103 gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0|UINT32|0x0000002C
104
105 ## SP805 Watchdog
106 gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x0|UINT32|0x00000023
107 gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|32000|UINT32|0x00000021
108
109 ## PL011 UART
110 gArmPlatformTokenSpaceGuid.PL011UartClkInHz|24000000|UINT32|0x0000001F
111 gArmPlatformTokenSpaceGuid.PL011UartInteger|0|UINT32|0x00000020
112 gArmPlatformTokenSpaceGuid.PL011UartFractional|0|UINT32|0x0000002D
113
114 ## PL061 GPIO
115 gArmPlatformTokenSpaceGuid.PcdPL061GpioBase|0x0|UINT32|0x00000025
116
117 ## PL111 Lcd & HdLcd
118 gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x0|UINT32|0x00000026
119 gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0|UINT32|0x00000027
120
121 ## PL180 MCI
122 gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x00000000|UINT32|0x00000028
123 gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x00000000|UINT32|0x00000029
124
125 #
126 # BDS - Boot Manager
127 #
128 gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Platform"|VOID*|0x00000019
129 gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Default Boot Device"|VOID*|0x0000000C
130 gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L""|VOID*|0x0000000D
131 gArmPlatformTokenSpaceGuid.PcdDefaultBootInitrdPath|L""|VOID*|0x0000000E
132 gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|L""|VOID*|0x000000F
133 # PcdDefaultBootType define the type of the binary pointed by PcdDefaultBootDevicePath:
134 # - 0 = an EFI application
135 # - 1 = a Linux kernel with ATAG support
136 # - 2 = a Linux kernel with FDT support
137 gArmPlatformTokenSpaceGuid.PcdDefaultBootType|0|UINT32|0x00000010
138 gArmPlatformTokenSpaceGuid.PcdFdtDevicePath|L""|VOID*|0x00000011
139
140 ## Timeout value for displaying progressing bar in before boot OS.
141 # According to UEFI 2.0 spec, the default TimeOut should be 0xffff.
142 gArmPlatformTokenSpaceGuid.PcdPlatformBootTimeOut|0xffff|UINT16|0x0000001A
143
144 gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L""|VOID*|0x0000001B
145 gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L""|VOID*|0x0000001C
146
147 [PcdsFixedAtBuild.common,PcdsDynamic.common]
148 ## PL031 RealTimeClock
149 gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024
150 gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022
151
152 #
153 # Inclusive range of allowed PCI buses.
154 #
155 gArmPlatformTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x0000003E
156 gArmPlatformTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000003F
157
158 #
159 # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.
160 # Note that "IO" is just another MMIO range that simulates IO space; there
161 # are no special instructions to access it.
162 #
163 # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are
164 # specific to their containing address spaces. In order to get the physical
165 # address for the CPU, for a given access, the respective translation value
166 # has to be added.
167 #
168 # The translations always have to be initialized like this, using UINT64:
169 #
170 # UINT64 IoCpuBase; // mapping target in 64-bit cpu-physical space
171 # UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space
172 # UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space
173 #
174 # PcdPciIoTranslation = IoCpuBase - PcdPciIoBase;
175 # PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;
176 # PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;
177 #
178 # because (a) the target address space (ie. the cpu-physical space) is
179 # 64-bit, and (b) the translation values are meant as offsets for *modular*
180 # arithmetic.
181 #
182 # Accordingly, the translation itself needs to be implemented as:
183 #
184 # UINT64 UntranslatedIoAddress; // input parameter
185 # UINT32 UntranslatedMmio32Address; // input parameter
186 # UINT64 UntranslatedMmio64Address; // input parameter
187 #
188 # UINT64 TranslatedIoAddress; // output parameter
189 # UINT64 TranslatedMmio32Address; // output parameter
190 # UINT64 TranslatedMmio64Address; // output parameter
191 #
192 # TranslatedIoAddress = UntranslatedIoAddress +
193 # PcdPciIoTranslation;
194 # TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +
195 # PcdPciMmio32Translation;
196 # TranslatedMmio64Address = UntranslatedMmio64Address +
197 # PcdPciMmio64Translation;
198 #
199 # The modular arithmetic performed in UINT64 ensures that the translation
200 # works correctly regardless of the relation between IoCpuBase and
201 # PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and
202 # PcdPciMmio64Base.
203 #
204 gArmPlatformTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000040
205 gArmPlatformTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000041
206 gArmPlatformTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000042
207 gArmPlatformTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000043
208 gArmPlatformTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000044
209 gArmPlatformTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000045
210 gArmPlatformTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000046
211 gArmPlatformTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000047
212 gArmPlatformTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000048
213
214 [PcdsFixedAtBuild.ARM]
215 # Stack for CPU Cores in Secure Monitor Mode
216 gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007
217 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x1000|UINT32|0x00000008
218
219 [PcdsFixedAtBuild.AARCH64]
220 # The Secure World is only running in EL3. Only one set of stacks is needed for AArch64.
221 # The Secure stacks are described by PcdCPUCoresSecStackBase, PcdCPUCoreSecPrimaryStackSize
222 # and PcdCPUCoreSecSecondaryStackSize
223 gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007
224 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x0|UINT32|0x00000008
225