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1 #/** @file
2 #
3 # Copyright (c) 2011-2018, ARM Limited. All rights reserved.
4 # Copyright (c) 2015, Intel Corporation. All rights reserved.
5 #
6 # SPDX-License-Identifier: BSD-2-Clause-Patent
7 #
8 #**/
9
10 [Defines]
11 DEC_SPECIFICATION = 0x00010005
12 PACKAGE_NAME = ArmPlatformPkg
13 PACKAGE_GUID = 3308e0a0-1d94-11e0-915c-0002a5d5c51b
14 PACKAGE_VERSION = 0.1
15
16 ################################################################################
17 #
18 # Include Section - list of Include Paths that are provided by this package.
19 # Comments are used for Keywords and Module Types.
20 #
21 # Supported Module Types:
22 # BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
23 #
24 ################################################################################
25 [Includes.common]
26 Include # Root include for the package
27
28 [LibraryClasses]
29 ArmPlatformLib|Include/Library/ArmPlatformLib.h
30 LcdHwLib|Include/Library/LcdHwLib.h
31 LcdPlatformLib|Include/Library/LcdPlatformLib.h
32 NorFlashPlatformLib|Include/Library/NorFlashPlatformLib.h
33 PL011UartClockLib|Include/Library/PL011UartClockLib.h
34 PL011UartLib|Include/Library/PL011UartLib.h
35
36 [Guids.common]
37 gArmPlatformTokenSpaceGuid = { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }
38
39 [PcdsFeatureFlag.common]
40 gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004
41
42 gArmPlatformTokenSpaceGuid.PcdNorFlashCheckBlockLocked|FALSE|BOOLEAN|0x0000003C
43
44 # Disable the GOP controller on ExitBootServices(). By default the value is FALSE,
45 # we assume the OS will handle the FrameBuffer from the UEFI GOP information.
46 gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices|FALSE|BOOLEAN|0x0000003D
47
48 [PcdsFixedAtBuild.common]
49 gArmPlatformTokenSpaceGuid.PcdCoreCount|1|UINT32|0x00000039
50 gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038
51
52 # Stack for CPU Cores in Non Secure Mode
53 gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT64|0x00000009
54 gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000|UINT32|0x00000037
55 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000|UINT32|0x0000000A
56
57 # Size of the region used by UEFI in permanent memory (Reserved 128MB by default)
58 gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000|UINT32|0x00000015
59
60 #
61 # ARM Primecells
62 #
63
64 ## SP805 Watchdog
65 gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x0|UINT32|0x00000023
66 gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|32000|UINT32|0x00000021
67 gArmPlatformTokenSpaceGuid.PcdSP805WatchdogInterrupt|0|UINT32|0x0000002E
68
69 ## PL011 UART
70 gArmPlatformTokenSpaceGuid.PL011UartClkInHz|24000000|UINT32|0x0000001F
71 gArmPlatformTokenSpaceGuid.PL011UartInteger|0|UINT32|0x00000020
72 gArmPlatformTokenSpaceGuid.PL011UartFractional|0|UINT32|0x0000002D
73 gArmPlatformTokenSpaceGuid.PL011UartInterrupt|0x00000000|UINT32|0x0000002F
74 gArmPlatformTokenSpaceGuid.PL011UartRegOffsetVariant|0|UINT8|0x0000003E
75
76 ## PL011 Serial Debug UART
77 gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x00000000|UINT64|0x00000030
78 gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate|0x00000000|UINT64|0x00000031
79 gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz|0x00000000|UINT32|0x00000032
80
81 ## PL061 GPIO
82 gArmPlatformTokenSpaceGuid.PcdPL061GpioBase|0x0|UINT32|0x00000025
83
84 ## PL111 Lcd & HdLcd
85 gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x0|UINT32|0x00000026
86 gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0|UINT32|0x00000027
87
88 ## Default size for display modes upto 1920x1080 (1920 * 1080 * 4 Bytes Per Pixel)
89 gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferSize|0x7E9000|UINT32|0x00000043
90 ## If set, framebuffer memory will be reserved and mapped in the system RAM
91 gArmPlatformTokenSpaceGuid.PcdArmLcdDdrFrameBufferBase|0x0|UINT64|0x00000044
92
93 ## ARM Mali Display Processor DP500/DP550/DP650
94 gArmPlatformTokenSpaceGuid.PcdArmMaliDpBase|0x0|UINT64|0x00000050
95 gArmPlatformTokenSpaceGuid.PcdArmMaliDpMemoryRegionLength|0x0|UINT32|0x00000051
96
97 # Graphics Output Pixel format
98 # 0 : PixelRedGreenBlueReserved8BitPerColor
99 # 1 : PixelBlueGreenRedReserved8BitPerColor
100 # 2 : PixelBitMask
101 # Default is set to UEFI console font format PixelBlueGreenRedReserved8BitPerColor
102 gArmPlatformTokenSpaceGuid.PcdGopPixelFormat|0x00000001|UINT32|0x00000040
103
104 ## If set, this will swap settings for HDLCD RED_SELECT and BLUE_SELECT registers
105 gArmPlatformTokenSpaceGuid.PcdArmHdLcdSwapBlueRedSelect|FALSE|BOOLEAN|0x00000045
106
107 [PcdsFixedAtBuild.common,PcdsDynamic.common]
108 ## PL031 RealTimeClock
109 gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024
110 gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022
111
112 gArmPlatformTokenSpaceGuid.PcdWatchdogCount|0x0|UINT32|0x00000033