ArmPlatformPkg: remove ArmPlatformInitializeSystemMemory
[mirror_edk2.git] / ArmPlatformPkg / ArmPlatformPkg.dec
1 #/** @file
2 #
3 # Copyright (c) 2011-2017, ARM Limited. All rights reserved.
4 # Copyright (c) 2015, Intel Corporation. All rights reserved.
5 #
6 # This program and the accompanying materials
7 # are licensed and made available under the terms and conditions of the BSD License
8 # which accompanies this distribution. The full text of the license may be found at
9 # http://opensource.org/licenses/bsd-license.php
10 #
11 # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 #
14 #**/
15
16 [Defines]
17 DEC_SPECIFICATION = 0x00010005
18 PACKAGE_NAME = ArmPlatformPkg
19 PACKAGE_GUID = 3308e0a0-1d94-11e0-915c-0002a5d5c51b
20 PACKAGE_VERSION = 0.1
21
22 ################################################################################
23 #
24 # Include Section - list of Include Paths that are provided by this package.
25 # Comments are used for Keywords and Module Types.
26 #
27 # Supported Module Types:
28 # BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
29 #
30 ################################################################################
31 [Includes.common]
32 Include # Root include for the package
33
34 [LibraryClasses]
35 PL011UartLib|Include/Library/PL011UartLib.h
36
37 [Guids.common]
38 gArmPlatformTokenSpaceGuid = { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }
39 #
40 # Following Guid must match FILE_GUID in MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
41 #
42 gVariableRuntimeDxeFileGuid = { 0xcbd2e4d5, 0x7068, 0x4ff5, { 0xb4, 0x62, 0x98, 0x22, 0xb4, 0xad, 0x8d, 0x60 } }
43
44 gArmBootMonFsFileInfoGuid = { 0x41e26b9c, 0xada6, 0x45b3, { 0x80, 0x8e, 0x23, 0x57, 0xa3, 0x5b, 0x60, 0xd6 } }
45
46 [PcdsFeatureFlag.common]
47 # Set this PCD to TRUE to map NORFlash at 0x0. FALSE means the DRAM is mapped at 0x0.
48 gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping|FALSE|BOOLEAN|0x00000012
49
50 gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE|BOOLEAN|0x00000001
51 gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004
52
53 gArmPlatformTokenSpaceGuid.PcdNorFlashCheckBlockLocked|FALSE|BOOLEAN|0x0000003C
54
55 # Disable the GOP controller on ExitBootServices(). By default the value is FALSE,
56 # we assume the OS will handle the FrameBuffer from the UEFI GOP information.
57 gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices|FALSE|BOOLEAN|0x0000003D
58
59 # Enable Legacy Linux support in the BDS
60 gArmPlatformTokenSpaceGuid.PcdBdsLinuxSupport|FALSE|BOOLEAN|0x0000002E
61
62 [PcdsFixedAtBuild.common]
63 gArmPlatformTokenSpaceGuid.PcdCoreCount|1|UINT32|0x00000039
64 gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038
65
66 # Stack for CPU Cores in Secure Mode
67 gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT64|0x00000005
68 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000|UINT32|0x00000036
69 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000|UINT32|0x00000006
70
71 # Stack for CPU Cores in Non Secure Mode
72 gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT64|0x00000009
73 gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000|UINT32|0x00000037
74 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000|UINT32|0x0000000A
75
76 # Size of the region used by UEFI in permanent memory (Reserved 128MB by default)
77 gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000|UINT32|0x00000015
78
79 # Boot Monitor FileSystem
80 gArmPlatformTokenSpaceGuid.PcdBootMonFsSupportedDevicePaths|L""|VOID*|0x0000003A
81
82 #
83 # ARM Primecells
84 #
85
86 ## SP804 DualTimer
87 gArmPlatformTokenSpaceGuid.PcdSP804TimerFrequencyInMHz|1|UINT32|0x0000001D
88 gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|0|UINT32|0x0000001E
89 gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0|UINT32|0x0000002A
90 gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0|UINT32|0x0000002B
91 gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0|UINT32|0x0000002C
92
93 ## SP805 Watchdog
94 gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x0|UINT32|0x00000023
95 gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|32000|UINT32|0x00000021
96
97 ## PL011 UART
98 gArmPlatformTokenSpaceGuid.PL011UartClkInHz|24000000|UINT32|0x0000001F
99 gArmPlatformTokenSpaceGuid.PL011UartInteger|0|UINT32|0x00000020
100 gArmPlatformTokenSpaceGuid.PL011UartFractional|0|UINT32|0x0000002D
101 gArmPlatformTokenSpaceGuid.PL011UartInterrupt|0x00000000|UINT32|0x0000002F
102 gArmPlatformTokenSpaceGuid.PL011UartRegOffsetVariant|0|UINT8|0x0000003E
103
104 ## PL011 Serial Debug UART
105 gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x00000000|UINT64|0x00000030
106 gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate|0x00000000|UINT64|0x00000031
107 gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz|0x00000000|UINT32|0x00000032
108
109 ## PL061 GPIO
110 gArmPlatformTokenSpaceGuid.PcdPL061GpioBase|0x0|UINT32|0x00000025
111
112 ## PL111 Lcd & HdLcd
113 gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x0|UINT32|0x00000026
114 gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0|UINT32|0x00000027
115
116 ## PL180 MCI
117 gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x00000000|UINT32|0x00000028
118 gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x00000000|UINT32|0x00000029
119
120 #
121 # BDS - Boot Manager
122 #
123 gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Platform"|VOID*|0x00000019
124 gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Default Boot Device"|VOID*|0x0000000C
125 gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L""|VOID*|0x0000000D
126 gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|L""|VOID*|0x000000F
127
128 gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L""|VOID*|0x0000001B
129 gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L""|VOID*|0x0000001C
130
131 [PcdsFixedAtBuild.common,PcdsDynamic.common]
132 ## PL031 RealTimeClock
133 gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024
134 gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022
135
136 gArmPlatformTokenSpaceGuid.PcdWatchdogCount|0x0|UINT32|0x00000033
137
138 [PcdsFixedAtBuild.ARM]
139 # Stack for CPU Cores in Secure Monitor Mode
140 gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT64|0x00000007
141 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x1000|UINT32|0x00000008
142
143 [PcdsFixedAtBuild.AARCH64]
144 # The Secure World is only running in EL3. Only one set of stacks is needed for AArch64.
145 # The Secure stacks are described by PcdCPUCoresSecStackBase, PcdCPUCoreSecPrimaryStackSize
146 # and PcdCPUCoreSecSecondaryStackSize
147 gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT64|0x00000007
148 gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x0|UINT32|0x00000008
149