ArmPlatformPkg/ArmPlatformPkg.dec

   1 #/** @file
   2 #
   3 #  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
   4 #  Copyright (c) 2015, Intel Corporation. All rights reserved.
   5 #
   6 #  This program and the accompanying materials
   7 #  are licensed and made available under the terms and conditions of the BSD License
   8 #  which accompanies this distribution.  The full text of the license may be found at
   9 #  http://opensource.org/licenses/bsd-license.php
  10 #
  11 #  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12 #  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13 #
  14 #**/
  15
  16 [Defines]
  17   DEC_SPECIFICATION              = 0x00010005
  18   PACKAGE_NAME                   = ArmPlatformPkg
  19   PACKAGE_GUID                   = 3308e0a0-1d94-11e0-915c-0002a5d5c51b
  20   PACKAGE_VERSION                = 0.1
  21
  22 ################################################################################
  23 #
  24 # Include Section - list of Include Paths that are provided by this package.
  25 #                   Comments are used for Keywords and Module Types.
  26 #
  27 # Supported Module Types:
  28 #  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
  29 #
  30 ################################################################################
  31 [Includes.common]
  32   Include                        # Root include for the package
  33
  34 [Guids.common]
  35   gArmPlatformTokenSpaceGuid   = { 0x9c0aaed4, 0x74c5, 0x4043, { 0xb4, 0x17, 0xa3, 0x22, 0x38, 0x14, 0xce, 0x76 } }
  36   #
  37   # Following Guid must match FILE_GUID in MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
  38   #
  39   gVariableRuntimeDxeFileGuid = { 0xcbd2e4d5, 0x7068, 0x4ff5, { 0xb4, 0x62, 0x98, 0x22, 0xb4, 0xad, 0x8d, 0x60 } }
  40
  41   ## Include/Guid/ArmGlobalVariableHob.h
  42   gArmGlobalVariableGuid      = { 0xc3253c90, 0xa24f, 0x4599, { 0xa6, 0x64, 0x1f, 0x88, 0x13, 0x77, 0x8f, 0xc9} }
  43
  44   gArmBootMonFsFileInfoGuid   = { 0x41e26b9c, 0xada6, 0x45b3, { 0x80, 0x8e, 0x23, 0x57, 0xa3, 0x5b, 0x60, 0xd6 } }
  45
  46 [Ppis]
  47   ## Include/Ppi/ArmGlobalVariable.h
  48   gArmGlobalVariablePpiGuid = { 0xab1c1816, 0xd542, 0x4e6f, {0x9b, 0x1e, 0x8e, 0xcd, 0x92, 0x53, 0xe2, 0xe7} }
  49
  50 [PcdsFeatureFlag.common]
  51   # Set this PCD to TRUE to map NORFlash at 0x0. FALSE means the DRAM is mapped at 0x0.
  52   gArmPlatformTokenSpaceGuid.PcdNorFlashRemapping|FALSE|BOOLEAN|0x00000012
  53
  54   gArmPlatformTokenSpaceGuid.PcdStandalone|TRUE|BOOLEAN|0x00000001
  55   gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|FALSE|BOOLEAN|0x00000002
  56   gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|FALSE|BOOLEAN|0x00000004
  57
  58   gArmPlatformTokenSpaceGuid.PcdNorFlashCheckBlockLocked|FALSE|BOOLEAN|0x0000003C
  59
  60   # Disable the GOP controller on ExitBootServices(). By default the value is FALSE,
  61   # we assume the OS will handle the FrameBuffer from the UEFI GOP information.
  62   gArmPlatformTokenSpaceGuid.PcdGopDisableOnExitBootServices|FALSE|BOOLEAN|0x0000003D
  63
  64   # Enable Legacy Linux support in the BDS
  65   gArmPlatformTokenSpaceGuid.PcdBdsLinuxSupport|TRUE|BOOLEAN|0x0000002E
  66
  67 [PcdsFixedAtBuild.common]
  68   gArmPlatformTokenSpaceGuid.PcdCoreCount|1|UINT32|0x00000039
  69   gArmPlatformTokenSpaceGuid.PcdClusterCount|1|UINT32|0x00000038
  70
  71   # Stack for CPU Cores in Secure Mode
  72   gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0|UINT32|0x00000005
  73   gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000|UINT32|0x00000036
  74   gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000|UINT32|0x00000006
  75
  76   # Stack for CPU Cores in Non Secure Mode
  77   gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0|UINT64|0x00000009
  78   gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x10000|UINT32|0x00000037
  79   gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000|UINT32|0x0000000A
  80
  81   # Size of the region used by UEFI in permanent memory (Reserved 128MB by default)
  82   gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x08000000|UINT32|0x00000015
  83
  84   # Size to reserve in the primary core stack for PEI Global Variables
  85   #  = sizeof(UINTN) /* PcdPeiServicePtr or HobListPtr */
  86   gArmPlatformTokenSpaceGuid.PcdPeiGlobalVariableSize|0x4|UINT32|0x00000016
  87   # PeiServicePtr and HobListPtr shares the same location in the PEI Global Variable list
  88   # PeiServicePtr is only valid with PEI Core and HobListPtr only when the PEI Core is skipped.
  89   gArmPlatformTokenSpaceGuid.PcdPeiServicePtrGlobalOffset|0x0|UINT32|0x00000017
  90   gArmPlatformTokenSpaceGuid.PcdHobListPtrGlobalOffset|0x0|UINT32|0x00000018
  91
  92   # Size to reserve in the primary core stack for SEC Global Variables
  93   gArmPlatformTokenSpaceGuid.PcdSecGlobalVariableSize|0x0|UINT32|0x00000031
  94
  95   # Boot Monitor FileSystem
  96   gArmPlatformTokenSpaceGuid.PcdBootMonFsSupportedDevicePaths|L""|VOID*|0x0000003A
  97
  98   #
  99   # ARM Primecells
 100   #
 101
 102   ## SP804 DualTimer
 103   gArmPlatformTokenSpaceGuid.PcdSP804TimerFrequencyInMHz|1|UINT32|0x0000001D
 104   gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|0|UINT32|0x0000001E
 105   gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0|UINT32|0x0000002A
 106   gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0|UINT32|0x0000002B
 107   gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0|UINT32|0x0000002C
 108
 109   ## SP805 Watchdog
 110   gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x0|UINT32|0x00000023
 111   gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|32000|UINT32|0x00000021
 112
 113   ## PL011 UART
 114   gArmPlatformTokenSpaceGuid.PL011UartClkInHz|24000000|UINT32|0x0000001F
 115   gArmPlatformTokenSpaceGuid.PL011UartInteger|0|UINT32|0x00000020
 116   gArmPlatformTokenSpaceGuid.PL011UartFractional|0|UINT32|0x0000002D
 117
 118   ## PL061 GPIO
 119   gArmPlatformTokenSpaceGuid.PcdPL061GpioBase|0x0|UINT32|0x00000025
 120
 121   ## PL111 Lcd & HdLcd
 122   gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x0|UINT32|0x00000026
 123   gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x0|UINT32|0x00000027
 124
 125   ## PL180 MCI
 126   gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x00000000|UINT32|0x00000028
 127   gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x00000000|UINT32|0x00000029
 128
 129   #
 130   # BDS - Boot Manager
 131   #
 132   gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Platform"|VOID*|0x00000019
 133   gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Default Boot Device"|VOID*|0x0000000C
 134   gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L""|VOID*|0x0000000D
 135   gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|L""|VOID*|0x000000F
 136
 137   gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L""|VOID*|0x0000001B
 138   gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L""|VOID*|0x0000001C
 139
 140 [PcdsFixedAtBuild.common,PcdsDynamic.common]
 141   ## PL031 RealTimeClock
 142   gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x0|UINT32|0x00000024
 143   gArmPlatformTokenSpaceGuid.PcdPL031RtcPpmAccuracy|300000000|UINT32|0x00000022
 144
 145   #
 146   # Inclusive range of allowed PCI buses.
 147   #
 148   gArmPlatformTokenSpaceGuid.PcdPciBusMin|0x0|UINT32|0x0000003E
 149   gArmPlatformTokenSpaceGuid.PcdPciBusMax|0x0|UINT32|0x0000003F
 150
 151   #
 152   # Bases, sizes and translation offsets of IO and MMIO spaces, respectively.
 153   # Note that "IO" is just another MMIO range that simulates IO space; there
 154   # are no special instructions to access it.
 155   #
 156   # The base addresses PcdPciIoBase, PcdPciMmio32Base and PcdPciMmio64Base are
 157   # specific to their containing address spaces. In order to get the physical
 158   # address for the CPU, for a given access, the respective translation value
 159   # has to be added.
 160   #
 161   # The translations always have to be initialized like this, using UINT64:
 162   #
 163   #   UINT64 IoCpuBase;     // mapping target in 64-bit cpu-physical space
 164   #   UINT64 Mmio32CpuBase; // mapping target in 64-bit cpu-physical space
 165   #   UINT64 Mmio64CpuBase; // mapping target in 64-bit cpu-physical space
 166   #
 167   #   PcdPciIoTranslation     = IoCpuBase     - PcdPciIoBase;
 168   #   PcdPciMmio32Translation = Mmio32CpuBase - (UINT64)PcdPciMmio32Base;
 169   #   PcdPciMmio64Translation = Mmio64CpuBase - PcdPciMmio64Base;
 170   #
 171   # because (a) the target address space (ie. the cpu-physical space) is
 172   # 64-bit, and (b) the translation values are meant as offsets for *modular*
 173   # arithmetic.
 174   #
 175   # Accordingly, the translation itself needs to be implemented as:
 176   #
 177   #   UINT64 UntranslatedIoAddress;     // input parameter
 178   #   UINT32 UntranslatedMmio32Address; // input parameter
 179   #   UINT64 UntranslatedMmio64Address; // input parameter
 180   #
 181   #   UINT64 TranslatedIoAddress;       // output parameter
 182   #   UINT64 TranslatedMmio32Address;   // output parameter
 183   #   UINT64 TranslatedMmio64Address;   // output parameter
 184   #
 185   #   TranslatedIoAddress     = UntranslatedIoAddress +
 186   #                             PcdPciIoTranslation;
 187   #   TranslatedMmio32Address = (UINT64)UntranslatedMmio32Address +
 188   #                             PcdPciMmio32Translation;
 189   #   TranslatedMmio64Address = UntranslatedMmio64Address +
 190   #                             PcdPciMmio64Translation;
 191   #
 192   #  The modular arithmetic performed in UINT64 ensures that the translation
 193   #  works correctly regardless of the relation between IoCpuBase and
 194   #  PcdPciIoBase, Mmio32CpuBase and PcdPciMmio32Base, and Mmio64CpuBase and
 195   #  PcdPciMmio64Base.
 196   #
 197   gArmPlatformTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x00000040
 198   gArmPlatformTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x00000041
 199   gArmPlatformTokenSpaceGuid.PcdPciIoTranslation|0x0|UINT64|0x00000042
 200   gArmPlatformTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT32|0x00000043
 201   gArmPlatformTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT32|0x00000044
 202   gArmPlatformTokenSpaceGuid.PcdPciMmio32Translation|0x0|UINT64|0x00000045
 203   gArmPlatformTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x00000046
 204   gArmPlatformTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x00000047
 205   gArmPlatformTokenSpaceGuid.PcdPciMmio64Translation|0x0|UINT64|0x00000048
 206
 207 [PcdsFixedAtBuild.ARM]
 208   # Stack for CPU Cores in Secure Monitor Mode
 209   gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007
 210   gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x1000|UINT32|0x00000008
 211
 212 [PcdsFixedAtBuild.AARCH64]
 213   # The Secure World is only running in EL3. Only one set of stacks is needed for AArch64.
 214   # The Secure stacks are described by PcdCPUCoresSecStackBase, PcdCPUCoreSecPrimaryStackSize
 215   # and PcdCPUCoreSecSecondaryStackSize
 216   gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0|UINT32|0x00000007
 217   gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x0|UINT32|0x00000008
 218