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1 /** @file
2 * Header defining RealView EB constants (Base addresses, sizes, flags)
3 *
4 * Copyright (c) 2011, ARM Limited. All rights reserved.
5 *
6 * This program and the accompanying materials
7 * are licensed and made available under the terms and conditions of the BSD License
8 * which accompanies this distribution. The full text of the license may be found at
9 * http://opensource.org/licenses/bsd-license.php
10 *
11 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
13 *
14 **/
15
16 #ifndef __ARM_EB_H__
17 #define __ARM_EB_H__
18
19 /*******************************************
20 // Platform Memory Map
21 *******************************************/
22
23 // Can be NOR, DOC, DRAM, SRAM
24 #define ARM_EB_REMAP_BASE 0x00000000
25 #define ARM_EB_REMAP_SZ 0x04000000
26
27 // Motherboard Peripheral and On-chip peripheral
28 #define ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE 0x10000000
29 #define ARM_EB_SMB_MB_ON_CHIP_PERIPH_SZ 0x00100000
30 #define ARM_EB_BOARD_PERIPH_BASE 0x10000000
31 //#define ARM_EB_CHIP_PERIPH_BASE 0x10020000
32
33 // SMC
34 #define ARM_EB_SMC_BASE 0x40000000
35 #define ARM_EB_SMC_SZ 0x20000000
36
37 // NOR Flash 1
38 #define ARM_EB_SMB_NOR_BASE 0x40000000
39 #define ARM_EB_SMB_NOR_SZ 0x04000000 /* 64 MB */
40 // DOC Flash
41 #define ARM_EB_SMB_DOC_BASE 0x44000000
42 #define ARM_EB_SMB_DOC_SZ 0x04000000 /* 64 MB */
43 // SRAM
44 #define ARM_EB_SMB_SRAM_BASE 0x48000000
45 #define ARM_EB_SMB_SRAM_SZ 0x02000000 /* 32 MB */
46 // USB, Ethernet, VRAM
47 #define ARM_EB_SMB_PERIPH_BASE 0x4E000000
48 //#define ARM_EB_SMB_PERIPH_VRAM 0x4C000000
49 #define ARM_EB_SMB_PERIPH_SZ 0x02000000 /* 32 MB */
50
51 // DRAM
52 #define ARM_EB_DRAM_BASE 0x70000000
53 #define ARM_EB_DRAM_SZ 0x10000000
54
55 // Logic Tile
56 #define ARM_EB_LOGIC_TILE_BASE 0xC0000000
57 #define ARM_EB_LOGIC_TILE_SZ 0x40000000
58
59 /*******************************************
60 // Motherboard peripherals
61 *******************************************/
62
63 // Define MotherBoard SYS flags offsets (from ARM_EB_BOARD_PERIPH_BASE)
64 #define ARM_EB_SYS_FLAGS_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00030)
65 #define ARM_EB_SYS_FLAGS_SET_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00030)
66 #define ARM_EB_SYS_FLAGS_CLR_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00034)
67 #define ARM_EB_SYS_FLAGS_NV_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00038)
68 #define ARM_EB_SYS_FLAGS_NV_SET_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00038)
69 #define ARM_EB_SYS_FLAGS_NV_CLR_REG (ARM_EB_BOARD_PERIPH_BASE + 0x0003C)
70 #define ARM_EB_SYS_PROCID0_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00084)
71 #define ARM_EB_SYS_PROCID1_REG (ARM_EB_BOARD_PERIPH_BASE + 0x00088)
72 #define ARM_EB_SYS_CFGDATA_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A0)
73 #define ARM_EB_SYS_CFGCTRL_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A4)
74 #define ARM_EB_SYS_CFGSTAT_REG (ARM_EB_BOARD_PERIPH_BASE + 0x000A8)
75
76 // SP810 Controller
77 #define SP810_CTRL_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x01000)
78
79 // SYSTRCL Register
80 #define ARM_EB_SYSCTRL 0x10001000
81
82 // Uart0
83 #define PL011_CONSOLE_UART_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x09000)
84 #define PL011_CONSOLE_UART_SPEED 115200
85
86 // SP804 Timer Bases
87 #define SP804_TIMER0_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x11000)
88 #define SP804_TIMER1_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x11020)
89 #define SP804_TIMER2_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x12000)
90 #define SP804_TIMER3_BASE (ARM_EB_BOARD_PERIPH_BASE + 0x12020)
91
92 // Dynamic Memory Controller Base
93 #define ARM_EB_DMC_BASE 0x10018000
94
95 // Static Memory Controller Base
96 #define ARM_EB_SMC_CTRL_BASE 0x10080000
97
98 /*// System Configuration Controller register Base addresses
99 //#define ARM_EB_SYS_CFG_CTRL_BASE 0x100E2000
100 #define ARM_EB_SYS_CFGRW0_REG 0x100E2000
101 #define ARM_EB_SYS_CFGRW1_REG 0x100E2004
102 #define ARM_EB_SYS_CFGRW2_REG 0x100E2008
103
104 #define ARM_EB_CFGRW1_REMAP_NOR0 0
105 #define ARM_EB_CFGRW1_REMAP_NOR1 (1 << 28)
106 #define ARM_EB_CFGRW1_REMAP_EXT_AXI (1 << 29)
107 #define ARM_EB_CFGRW1_REMAP_DRAM (1 << 30)
108
109 // PL301 Fast AXI Base Address
110 #define ARM_EB_FAXI_BASE 0x100E9000
111
112 // L2x0 Cache Controller Base Address
113 //#define ARM_EB_L2x0_CTLR_BASE 0x1E00A000*/
114
115
116 /*******************************************
117 // Interrupt Map
118 *******************************************/
119
120 // Timer Interrupts
121 #define TIMER01_INTERRUPT_NUM 34
122 #define TIMER23_INTERRUPT_NUM 35
123
124
125 /*******************************************
126 // EFI Memory Map in Permanent Memory (DRAM)
127 *******************************************/
128
129 // This region is allocated at the bottom of the DRAM. It will be used
130 // for fixed address allocations such as Vector Table
131 #define ARM_EB_EFI_FIX_ADDRESS_REGION_SZ SIZE_8MB
132
133 // This region is the memory declared to PEI as permanent memory for PEI
134 // and DXE. EFI stacks and heaps will be declared in this region.
135 #define ARM_EB_EFI_MEMORY_REGION_SZ 0x1000000
136
137 #endif