cb92bf00a281fedd0f657f20088f78d80e583356
[mirror_edk2.git] / ArmPlatformPkg / ArmRealViewEbPkg / Library / ArmRealViewEbLibRTSM / ArmRealViewEb.c
1 /** @file
2 *
3 * Copyright (c) 2011, ARM Limited. All rights reserved.
4 *
5 * This program and the accompanying materials
6 * are licensed and made available under the terms and conditions of the BSD License
7 * which accompanies this distribution. The full text of the license may be found at
8 * http://opensource.org/licenses/bsd-license.php
9 *
10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12 *
13 **/
14
15 #include <Library/IoLib.h>
16 #include <Library/ArmPlatformLib.h>
17 #include <Library/DebugLib.h>
18 #include <Library/PcdLib.h>
19
20 #include <Drivers/PL341Dmc.h>
21 #include <Drivers/SP804Timer.h>
22
23 #include <Ppi/ArmMpCoreInfo.h>
24
25 #include <ArmPlatform.h>
26
27 ARM_CORE_INFO mRealViewEbMpCoreInfoTable[] = {
28 {
29 // Cluster 0, Core 0
30 0x0, 0x0,
31
32 // MP Core MailBox Set/Get/Clear Addresses and Clear Value
33 (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_REG,
34 (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_SET_REG,
35 (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_CLR_REG,
36 (UINT64)0xFFFFFFFF
37 },
38 {
39 // Cluster 0, Core 1
40 0x0, 0x1,
41
42 // MP Core MailBox Set/Get/Clear Addresses and Clear Value
43 (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_REG,
44 (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_SET_REG,
45 (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_CLR_REG,
46 (UINT64)0xFFFFFFFF
47 }
48 };
49
50 /**
51 Return the current Boot Mode
52
53 This function returns the boot reason on the platform
54
55 **/
56 EFI_BOOT_MODE
57 ArmPlatformGetBootMode (
58 VOID
59 )
60 {
61 return BOOT_WITH_FULL_CONFIGURATION;
62 }
63
64 /**
65 Initialize controllers that must setup in the normal world
66
67 This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
68 in the PEI phase.
69
70 **/
71 VOID
72 ArmPlatformNormalInitialize (
73 VOID
74 )
75 {
76 // Disable memory remapping and return to normal mapping
77 MmioOr32 (ARM_EB_SYSCTRL, BIT8); //EB_SP810_CTRL_BASE
78
79 // Configure periodic timer (TIMER0) for 1MHz operation
80 MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK);
81 // Configure 1MHz clock
82 MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK);
83 // configure SP810 to use 1MHz clock and disable
84 MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);
85 // Configure SP810 to use 1MHz clock and disable
86 MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);
87 }
88
89 /**
90 Initialize the system (or sometimes called permanent) memory
91
92 This memory is generally represented by the DRAM.
93
94 **/
95 VOID
96 ArmPlatformInitializeSystemMemory (
97 VOID
98 )
99 {
100 // We do not need to initialize the System Memory on RTSM
101 }
102
103 EFI_STATUS
104 PrePeiCoreGetMpCoreInfo (
105 OUT UINTN *CoreCount,
106 OUT ARM_CORE_INFO **ArmCoreTable
107 )
108 {
109 if ((MmioRead32 (ARM_EB_SYS_PROCID0_REG) & ARM_EB_SYS_PROC_ID_MASK) == ARM_EB_SYS_PROC_ID_CORTEX_A9) {
110 *CoreCount = sizeof(mRealViewEbMpCoreInfoTable) / sizeof(ARM_CORE_INFO);
111 *ArmCoreTable = mRealViewEbMpCoreInfoTable;
112 return EFI_SUCCESS;
113 } else {
114 return EFI_UNSUPPORTED;
115 }
116 }
117
118 // Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore
119 EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;
120 ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
121
122 EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
123 {
124 EFI_PEI_PPI_DESCRIPTOR_PPI,
125 &mArmMpCoreInfoPpiGuid,
126 &mMpCoreInfoPpi
127 }
128 };
129
130 VOID
131 ArmPlatformGetPlatformPpiList (
132 OUT UINTN *PpiListSize,
133 OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
134 )
135 {
136 *PpiListSize = sizeof(gPlatformPpiTable);
137 *PpiList = gPlatformPpiTable;
138 }
139