3 * Copyright (c) 2011-2013, ARM Limited. All rights reserved.
5 * This program and the accompanying materials
6 * are licensed and made available under the terms and conditions of the BSD License
7 * which accompanies this distribution. The full text of the license may be found at
8 * http://opensource.org/licenses/bsd-license.php
10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #include <Library/IoLib.h>
16 #include <Library/ArmPlatformLib.h>
17 #include <Library/DebugLib.h>
18 #include <Library/PcdLib.h>
20 #include <Drivers/PL341Dmc.h>
21 #include <Drivers/PL301Axi.h>
22 #include <Drivers/SP804Timer.h>
24 #include <Ppi/ArmMpCoreInfo.h>
26 #include <ArmPlatform.h>
28 ARM_CORE_INFO mVersatileExpressMpCoreInfoCTA9x4
[] = {
33 // MP Core MailBox Set/Get/Clear Addresses and Clear Value
34 (EFI_PHYSICAL_ADDRESS
)ARM_VE_SYS_FLAGS_REG
,
35 (EFI_PHYSICAL_ADDRESS
)ARM_VE_SYS_FLAGS_SET_REG
,
36 (EFI_PHYSICAL_ADDRESS
)ARM_VE_SYS_FLAGS_CLR_REG
,
43 // MP Core MailBox Set/Get/Clear Addresses and Clear Value
44 (EFI_PHYSICAL_ADDRESS
)ARM_VE_SYS_FLAGS_REG
,
45 (EFI_PHYSICAL_ADDRESS
)ARM_VE_SYS_FLAGS_SET_REG
,
46 (EFI_PHYSICAL_ADDRESS
)ARM_VE_SYS_FLAGS_CLR_REG
,
53 // MP Core MailBox Set/Get/Clear Addresses and Clear Value
54 (EFI_PHYSICAL_ADDRESS
)ARM_VE_SYS_FLAGS_REG
,
55 (EFI_PHYSICAL_ADDRESS
)ARM_VE_SYS_FLAGS_SET_REG
,
56 (EFI_PHYSICAL_ADDRESS
)ARM_VE_SYS_FLAGS_CLR_REG
,
63 // MP Core MailBox Set/Get/Clear Addresses and Clear Value
64 (EFI_PHYSICAL_ADDRESS
)ARM_VE_SYS_FLAGS_REG
,
65 (EFI_PHYSICAL_ADDRESS
)ARM_VE_SYS_FLAGS_SET_REG
,
66 (EFI_PHYSICAL_ADDRESS
)ARM_VE_SYS_FLAGS_CLR_REG
,
72 PL341_DMC_CONFIG DDRTimings
= {
75 .User0Cfg
= 0x7C924924,
76 .User2Cfg
= (TC_UIOLHXC_VALUE
<< TC_UIOLHNC_SHIFT
) | (TC_UIOLHXC_VALUE
<< TC_UIOLHPC_SHIFT
) | (0x1 << TC_UIOHOCT_SHIFT
) | (0x1 << TC_UIOHSTOP_SHIFT
),
78 .RefreshPeriod
= 0x3D0,
93 .MemoryCfg
= DMC_MEMORY_CONFIG_ACTIVE_CHIP_1
| DMC_MEMORY_CONFIG_BURST_4
|
94 DMC_MEMORY_CONFIG_ROW_ADDRESS_15
| DMC_MEMORY_CONFIG_COLUMN_ADDRESS_10
,
95 .MemoryCfg2
= DMC_MEMORY_CFG2_DQM_INIT
| DMC_MEMORY_CFG2_CKE_INIT
|
96 DMC_MEMORY_CFG2_BANK_BITS_3
| DMC_MEMORY_CFG2_MEM_WIDTH_32
,
97 .MemoryCfg3
= 0x00000001,
98 .ChipCfg0
= 0x00010000,
100 .ModeReg
= DDR2_MR_BURST_LENGTH_4
| DDR2_MR_CAS_LATENCY_4
| DDR2_MR_WR_CYCLES_4
,
101 .ExtModeReg
= DDR_EMR_RTT_50R
| (DDR_EMR_ODS_VAL
<< DDR_EMR_ODS_MASK
),
105 Return the current Boot Mode
107 This function returns the boot reason on the platform
109 @return Return the current Boot Mode of the platform
113 ArmPlatformGetBootMode (
117 if (MmioRead32(ARM_VE_SYS_FLAGS_NV_REG
) == 0) {
118 return BOOT_WITH_FULL_CONFIGURATION
;
120 return BOOT_ON_S2_RESUME
;
125 Initialize controllers that must setup in the normal world
127 This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
132 ArmPlatformInitialize (
136 if (!ArmPlatformIsPrimaryCore (MpId
)) {
137 return RETURN_SUCCESS
;
140 // Configure periodic timer (TIMER0) for 1MHz operation
141 MmioOr32 (SP810_CTRL_BASE
+ SP810_SYS_CTRL_REG
, SP810_SYS_CTRL_TIMER0_TIMCLK
);
142 // Configure 1MHz clock
143 MmioOr32 (SP810_CTRL_BASE
+ SP810_SYS_CTRL_REG
, SP810_SYS_CTRL_TIMER1_TIMCLK
);
144 // configure SP810 to use 1MHz clock and disable
145 MmioAndThenOr32 (SP810_CTRL_BASE
+ SP810_SYS_CTRL_REG
, ~SP810_SYS_CTRL_TIMER2_EN
, SP810_SYS_CTRL_TIMER2_TIMCLK
);
146 // Configure SP810 to use 1MHz clock and disable
147 MmioAndThenOr32 (SP810_CTRL_BASE
+ SP810_SYS_CTRL_REG
, ~SP810_SYS_CTRL_TIMER3_EN
, SP810_SYS_CTRL_TIMER3_TIMCLK
);
149 return RETURN_SUCCESS
;
153 Initialize the system (or sometimes called permanent) memory
155 This memory is generally represented by the DRAM.
159 ArmPlatformInitializeSystemMemory (
163 PL341DmcInit (ARM_VE_DMC_BASE
, &DDRTimings
);
164 PL301AxiInit (ARM_VE_FAXI_BASE
);
168 PrePeiCoreGetMpCoreInfo (
169 OUT UINTN
*CoreCount
,
170 OUT ARM_CORE_INFO
**ArmCoreTable
173 *CoreCount
= sizeof(mVersatileExpressMpCoreInfoCTA9x4
) / sizeof(ARM_CORE_INFO
);
174 *ArmCoreTable
= mVersatileExpressMpCoreInfoCTA9x4
;
179 // Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore
180 EFI_GUID mArmMpCoreInfoPpiGuid
= ARM_MP_CORE_INFO_PPI_GUID
;
181 ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi
= { PrePeiCoreGetMpCoreInfo
};
183 EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable
[] = {
185 EFI_PEI_PPI_DESCRIPTOR_PPI
,
186 &mArmMpCoreInfoPpiGuid
,
192 ArmPlatformGetPlatformPpiList (
193 OUT UINTN
*PpiListSize
,
194 OUT EFI_PEI_PPI_DESCRIPTOR
**PpiList
197 *PpiListSize
= sizeof(gPlatformPpiTable
);
198 *PpiList
= gPlatformPpiTable
;