ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c

   1 /** @file
   2 *
   3 *  Copyright (c) 2011, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #include <Library/IoLib.h>
  16 #include <Library/ArmTrustZoneLib.h>
  17 #include <Library/ArmPlatformLib.h>
  18 #include <Library/DebugLib.h>
  19 #include <Library/PcdLib.h>
  20 #include <Library/SerialPortLib.h>
  21
  22 #include <Drivers/PL341Dmc.h>
  23 #include <Drivers/PL301Axi.h>
  24 #include <Drivers/SP804Timer.h>
  25
  26 #include <Ppi/ArmMpCoreInfo.h>
  27
  28 #include <ArmPlatform.h>
  29
  30 #define SerialPrint(txt)  SerialPortWrite ((UINT8*)(txt), AsciiStrLen(txt)+1);
  31
  32 ARM_CORE_INFO mVersatileExpressMpCoreInfoCTA9x4[] = {
  33   {
  34     // Cluster 0, Core 0
  35     0x0, 0x0,
  36
  37     // MP Core MailBox Set/Get/Clear Addresses and Clear Value
  38     (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
  39     (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
  40     (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
  41     (UINT64)0xFFFFFFFF
  42   },
  43   {
  44     // Cluster 0, Core 1
  45     0x0, 0x1,
  46
  47     // MP Core MailBox Set/Get/Clear Addresses and Clear Value
  48     (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
  49     (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
  50     (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
  51     (UINT64)0xFFFFFFFF
  52   },
  53   {
  54     // Cluster 0, Core 2
  55     0x0, 0x2,
  56
  57     // MP Core MailBox Set/Get/Clear Addresses and Clear Value
  58     (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
  59     (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
  60     (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
  61     (UINT64)0xFFFFFFFF
  62   },
  63   {
  64     // Cluster 0, Core 3
  65     0x0, 0x3,
  66
  67     // MP Core MailBox Set/Get/Clear Addresses and Clear Value
  68     (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
  69     (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
  70     (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
  71     (UINT64)0xFFFFFFFF
  72   }
  73 };
  74
  75 // DDR2 timings
  76 PL341_DMC_CONFIG DDRTimings = {
  77   .MaxChip   = 1,
  78   .IsUserCfg = TRUE,
  79   .User0Cfg = 0x7C924924,
  80   .User2Cfg = (TC_UIOLHXC_VALUE << TC_UIOLHNC_SHIFT) | (TC_UIOLHXC_VALUE << TC_UIOLHPC_SHIFT) | (0x1 << TC_UIOHOCT_SHIFT) | (0x1 << TC_UIOHSTOP_SHIFT),
  81   .HasQos    = TRUE,
  82   .RefreshPeriod  = 0x3D0,
  83   .CasLatency  = 0x8,
  84   .WriteLatency  = 0x3,
  85   .t_mrd    = 0x2,
  86   .t_ras    = 0xA,
  87   .t_rc   = 0xE,
  88   .t_rcd    = 0x104,
  89   .t_rfc    = 0x2f32,
  90   .t_rp   = 0x14,
  91   .t_rrd    = 0x2,
  92   .t_wr   = 0x4,
  93   .t_wtr    = 0x2,
  94   .t_xp   = 0x2,
  95   .t_xsr    = 0xC8,
  96   .t_esr    = 0x14,
  97   .MemoryCfg   = DMC_MEMORY_CONFIG_ACTIVE_CHIP_1 | DMC_MEMORY_CONFIG_BURST_4 |
  98                         DMC_MEMORY_CONFIG_ROW_ADDRESS_15 | DMC_MEMORY_CONFIG_COLUMN_ADDRESS_10,
  99   .MemoryCfg2  = DMC_MEMORY_CFG2_DQM_INIT | DMC_MEMORY_CFG2_CKE_INIT |
 100             DMC_MEMORY_CFG2_BANK_BITS_3 | DMC_MEMORY_CFG2_MEM_WIDTH_32,
 101   .MemoryCfg3  = 0x00000001,
 102   .ChipCfg0    = 0x00010000,
 103   .t_faw    = 0x00000A0D,
 104   .ModeReg = DDR2_MR_BURST_LENGTH_4 | DDR2_MR_CAS_LATENCY_4 | DDR2_MR_WR_CYCLES_4,
 105   .ExtModeReg = DDR_EMR_RTT_50R | (DDR_EMR_ODS_VAL << DDR_EMR_ODS_MASK),
 106 };
 107
 108 /**
 109   Return the current Boot Mode
 110
 111   This function returns the boot reason on the platform
 112
 113   @return   Return the current Boot Mode of the platform
 114
 115 **/
 116 EFI_BOOT_MODE
 117 ArmPlatformGetBootMode (
 118   VOID
 119   )
 120 {
 121   if (MmioRead32(ARM_VE_SYS_FLAGS_NV_REG) == 0) {
 122     return BOOT_WITH_FULL_CONFIGURATION;
 123   } else {
 124     return BOOT_ON_S2_RESUME;
 125   }
 126 }
 127
 128 /**
 129   Initialize controllers that must setup in the normal world
 130
 131   This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
 132   in the PEI phase.
 133
 134 **/
 135 VOID
 136 ArmPlatformNormalInitialize (
 137   VOID
 138   )
 139 {
 140   // Configure periodic timer (TIMER0) for 1MHz operation
 141   MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK);
 142   // Configure 1MHz clock
 143   MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK);
 144   // configure SP810 to use 1MHz clock and disable
 145   MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);
 146   // Configure SP810 to use 1MHz clock and disable
 147   MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);
 148 }
 149
 150 /**
 151   Initialize the system (or sometimes called permanent) memory
 152
 153   This memory is generally represented by the DRAM.
 154
 155 **/
 156 VOID
 157 ArmPlatformInitializeSystemMemory (
 158   VOID
 159   )
 160 {
 161   UINT32 Value;
 162
 163   // Memory Map remapping
 164   if (FeaturePcdGet(PcdNorFlashRemapping)) {
 165     SerialPrint ("Secure ROM at 0x0\n\r");
 166   } else {
 167     Value = MmioRead32(ARM_VE_SYS_CFGRW1_REG); //Scc - CFGRW1
 168     // Remap the DRAM to 0x0
 169     MmioWrite32(ARM_VE_SYS_CFGRW1_REG, (Value & 0x0FFFFFFF) | ARM_VE_CFGRW1_REMAP_DRAM);
 170   }
 171
 172   PL341DmcInit(ARM_VE_DMC_BASE, &DDRTimings);
 173   PL301AxiInit(ARM_VE_FAXI_BASE);
 174 }
 175
 176 EFI_STATUS
 177 PrePeiCoreGetMpCoreInfo (
 178   OUT UINTN                   *CoreCount,
 179   OUT ARM_CORE_INFO           **ArmCoreTable
 180   )
 181 {
 182   *CoreCount    = sizeof(mVersatileExpressMpCoreInfoCTA9x4) / sizeof(ARM_CORE_INFO);
 183   *ArmCoreTable = mVersatileExpressMpCoreInfoCTA9x4;
 184
 185   return EFI_SUCCESS;
 186 }
 187
 188 // Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore
 189 EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;
 190 ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
 191
 192 EFI_PEI_PPI_DESCRIPTOR      gPlatformPpiTable[] = {
 193   {
 194     EFI_PEI_PPI_DESCRIPTOR_PPI,
 195     &mArmMpCoreInfoPpiGuid,
 196     &mMpCoreInfoPpi
 197   }
 198 };
 199
 200 VOID
 201 ArmPlatformGetPlatformPpiList (
 202   OUT UINTN                   *PpiListSize,
 203   OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList
 204   )
 205 {
 206   *PpiListSize = sizeof(gPlatformPpiTable);
 207   *PpiList = gPlatformPpiTable;
 208 }
 209