ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c

   1 /** @file
   2 *
   3 *  Copyright (c) 2011, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #include <Library/IoLib.h>
  16 #include <Library/ArmTrustZoneLib.h>
  17 #include <Library/ArmPlatformLib.h>
  18 #include <Library/DebugLib.h>
  19 #include <Library/PcdLib.h>
  20 #include <Library/SerialPortLib.h>
  21
  22 #include <Drivers/PL341Dmc.h>
  23 #include <Drivers/PL301Axi.h>
  24 #include <Drivers/SP804Timer.h>
  25
  26 #include <ArmPlatform.h>
  27
  28 #define SerialPrint(txt)  SerialPortWrite ((UINT8*)(txt), AsciiStrLen(txt)+1);
  29
  30 // DDR2 timings
  31 PL341_DMC_CONFIG DDRTimings = {
  32   .MaxChip   = 1,
  33   .IsUserCfg = TRUE,
  34   .User0Cfg = 0x7C924924,
  35   .User2Cfg = (TC_UIOLHXC_VALUE << TC_UIOLHNC_SHIFT) | (TC_UIOLHXC_VALUE << TC_UIOLHPC_SHIFT) | (0x1 << TC_UIOHOCT_SHIFT) | (0x1 << TC_UIOHSTOP_SHIFT),
  36   .HasQos    = TRUE,
  37   .RefreshPeriod  = 0x3D0,
  38   .CasLatency  = 0x8,
  39   .WriteLatency  = 0x3,
  40   .t_mrd    = 0x2,
  41   .t_ras    = 0xA,
  42   .t_rc   = 0xE,
  43   .t_rcd    = 0x104,
  44   .t_rfc    = 0x2f32,
  45   .t_rp   = 0x14,
  46   .t_rrd    = 0x2,
  47   .t_wr   = 0x4,
  48   .t_wtr    = 0x2,
  49   .t_xp   = 0x2,
  50   .t_xsr    = 0xC8,
  51   .t_esr    = 0x14,
  52   .MemoryCfg   = DMC_MEMORY_CONFIG_ACTIVE_CHIP_1 | DMC_MEMORY_CONFIG_BURST_4 |
  53                         DMC_MEMORY_CONFIG_ROW_ADDRESS_15 | DMC_MEMORY_CONFIG_COLUMN_ADDRESS_10,
  54   .MemoryCfg2  = DMC_MEMORY_CFG2_DQM_INIT | DMC_MEMORY_CFG2_CKE_INIT |
  55             DMC_MEMORY_CFG2_BANK_BITS_3 | DMC_MEMORY_CFG2_MEM_WIDTH_32,
  56   .MemoryCfg3  = 0x00000001,
  57   .ChipCfg0    = 0x00010000,
  58   .t_faw    = 0x00000A0D,
  59   .ModeReg = DDR2_MR_BURST_LENGTH_4 | DDR2_MR_CAS_LATENCY_4 | DDR2_MR_WR_CYCLES_4,
  60   .ExtModeReg = DDR_EMR_RTT_50R | (DDR_EMR_ODS_VAL << DDR_EMR_ODS_MASK),
  61 };
  62
  63 /**
  64   Return if Trustzone is supported by your platform
  65
  66   A non-zero value must be returned if you want to support a Secure World on your platform.
  67   ArmVExpressTrustzoneInit() will later set up the secure regions.
  68   This function can return 0 even if Trustzone is supported by your processor. In this case,
  69   the platform will continue to run in Secure World.
  70
  71   @return   A non-zero value if Trustzone supported.
  72
  73 **/
  74 UINTN
  75 ArmPlatformTrustzoneSupported (
  76   VOID
  77   )
  78 {
  79   return (MmioRead32(ARM_VE_SYS_CFGRW1_REG) & ARM_VE_CFGRW1_TZASC_EN_BIT_MASK);
  80 }
  81
  82 /**
  83   Return the current Boot Mode
  84
  85   This function returns the boot reason on the platform
  86
  87   @return   Return the current Boot Mode of the platform
  88
  89 **/
  90 EFI_BOOT_MODE
  91 ArmPlatformGetBootMode (
  92   VOID
  93   )
  94 {
  95   return BOOT_WITH_FULL_CONFIGURATION;
  96 }
  97
  98 /**
  99   Remap the memory at 0x0
 100
 101   Some platform requires or gives the ability to remap the memory at the address 0x0.
 102   This function can do nothing if this feature is not relevant to your platform.
 103
 104 **/
 105 VOID
 106 ArmPlatformBootRemapping (
 107   VOID
 108   )
 109 {
 110   UINT32 Value;
 111
 112   if (FeaturePcdGet(PcdNorFlashRemapping)) {
 113     SerialPrint ("Secure ROM at 0x0\n\r");
 114   } else {
 115     Value = MmioRead32(ARM_VE_SYS_CFGRW1_REG); //Scc - CFGRW1
 116     // Remap the DRAM to 0x0
 117     MmioWrite32(ARM_VE_SYS_CFGRW1_REG, (Value & 0x0FFFFFFF) | ARM_VE_CFGRW1_REMAP_DRAM);
 118   }
 119 }
 120
 121 /**
 122   Initialize controllers that must setup in the normal world
 123
 124   This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
 125   in the PEI phase.
 126
 127 **/
 128 VOID
 129 ArmPlatformNormalInitialize (
 130   VOID
 131   )
 132 {
 133   // Configure periodic timer (TIMER0) for 1MHz operation
 134   MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK);
 135   // Configure 1MHz clock
 136   MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK);
 137   // configure SP810 to use 1MHz clock and disable
 138   MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);
 139   // Configure SP810 to use 1MHz clock and disable
 140   MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);
 141 }
 142
 143 /**
 144   Initialize the system (or sometimes called permanent) memory
 145
 146   This memory is generally represented by the DRAM.
 147
 148 **/
 149 VOID
 150 ArmPlatformInitializeSystemMemory (
 151   VOID
 152   )
 153 {
 154   PL341DmcInit(ARM_VE_DMC_BASE, &DDRTimings);
 155   PL301AxiInit(ARM_VE_FAXI_BASE);
 156 }
 157 VOID
 158 ArmPlatformGetPlatformPpiList (
 159   OUT UINTN                   *PpiListSize,
 160   OUT EFI_PEI_PPI_DESCRIPTOR  **PpiList
 161   )
 162 {
 163   *PpiListSize = 0;
 164   *PpiList = NULL;
 165 }
 166