3 * Copyright (c) 2011, ARM Limited. All rights reserved.
5 * This program and the accompanying materials
6 * are licensed and made available under the terms and conditions of the BSD License
7 * which accompanies this distribution. The full text of the license may be found at
8 * http://opensource.org/licenses/bsd-license.php
10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
15 #include <Library/IoLib.h>
16 #include <Library/ArmTrustZoneLib.h>
17 #include <Library/ArmPlatformLib.h>
18 #include <Library/DebugLib.h>
19 #include <Library/PcdLib.h>
20 #include <Library/SerialPortLib.h>
22 #include <Drivers/PL341Dmc.h>
23 #include <Drivers/PL301Axi.h>
24 #include <Drivers/SP804Timer.h>
26 #include <Ppi/ArmMpCoreInfo.h>
28 #include <ArmPlatform.h>
30 #define SerialPrint(txt) SerialPortWrite ((UINT8*)(txt), AsciiStrLen(txt)+1);
32 ARM_CORE_INFO mVersatileExpressMpCoreInfoCTA9x4
[] = {
37 // MP Core MailBox Set/Get/Clear Addresses and Clear Value
38 (EFI_PHYSICAL_ADDRESS
)ARM_VE_SYS_FLAGS_REG
,
39 (EFI_PHYSICAL_ADDRESS
)ARM_VE_SYS_FLAGS_SET_REG
,
40 (EFI_PHYSICAL_ADDRESS
)ARM_VE_SYS_FLAGS_CLR_REG
,
47 // MP Core MailBox Set/Get/Clear Addresses and Clear Value
48 (EFI_PHYSICAL_ADDRESS
)ARM_VE_SYS_FLAGS_REG
,
49 (EFI_PHYSICAL_ADDRESS
)ARM_VE_SYS_FLAGS_SET_REG
,
50 (EFI_PHYSICAL_ADDRESS
)ARM_VE_SYS_FLAGS_CLR_REG
,
57 // MP Core MailBox Set/Get/Clear Addresses and Clear Value
58 (EFI_PHYSICAL_ADDRESS
)ARM_VE_SYS_FLAGS_REG
,
59 (EFI_PHYSICAL_ADDRESS
)ARM_VE_SYS_FLAGS_SET_REG
,
60 (EFI_PHYSICAL_ADDRESS
)ARM_VE_SYS_FLAGS_CLR_REG
,
67 // MP Core MailBox Set/Get/Clear Addresses and Clear Value
68 (EFI_PHYSICAL_ADDRESS
)ARM_VE_SYS_FLAGS_REG
,
69 (EFI_PHYSICAL_ADDRESS
)ARM_VE_SYS_FLAGS_SET_REG
,
70 (EFI_PHYSICAL_ADDRESS
)ARM_VE_SYS_FLAGS_CLR_REG
,
76 PL341_DMC_CONFIG DDRTimings
= {
79 .User0Cfg
= 0x7C924924,
80 .User2Cfg
= (TC_UIOLHXC_VALUE
<< TC_UIOLHNC_SHIFT
) | (TC_UIOLHXC_VALUE
<< TC_UIOLHPC_SHIFT
) | (0x1 << TC_UIOHOCT_SHIFT
) | (0x1 << TC_UIOHSTOP_SHIFT
),
82 .RefreshPeriod
= 0x3D0,
97 .MemoryCfg
= DMC_MEMORY_CONFIG_ACTIVE_CHIP_1
| DMC_MEMORY_CONFIG_BURST_4
|
98 DMC_MEMORY_CONFIG_ROW_ADDRESS_15
| DMC_MEMORY_CONFIG_COLUMN_ADDRESS_10
,
99 .MemoryCfg2
= DMC_MEMORY_CFG2_DQM_INIT
| DMC_MEMORY_CFG2_CKE_INIT
|
100 DMC_MEMORY_CFG2_BANK_BITS_3
| DMC_MEMORY_CFG2_MEM_WIDTH_32
,
101 .MemoryCfg3
= 0x00000001,
102 .ChipCfg0
= 0x00010000,
104 .ModeReg
= DDR2_MR_BURST_LENGTH_4
| DDR2_MR_CAS_LATENCY_4
| DDR2_MR_WR_CYCLES_4
,
105 .ExtModeReg
= DDR_EMR_RTT_50R
| (DDR_EMR_ODS_VAL
<< DDR_EMR_ODS_MASK
),
109 Return if Trustzone is supported by your platform
111 A non-zero value must be returned if you want to support a Secure World on your platform.
112 ArmVExpressTrustzoneInit() will later set up the secure regions.
113 This function can return 0 even if Trustzone is supported by your processor. In this case,
114 the platform will continue to run in Secure World.
116 @return A non-zero value if Trustzone supported.
120 ArmPlatformTrustzoneSupported (
124 return (MmioRead32(ARM_VE_SYS_CFGRW1_REG
) & ARM_VE_CFGRW1_TZASC_EN_BIT_MASK
);
128 Return the current Boot Mode
130 This function returns the boot reason on the platform
132 @return Return the current Boot Mode of the platform
136 ArmPlatformGetBootMode (
140 return BOOT_WITH_FULL_CONFIGURATION
;
144 Remap the memory at 0x0
146 Some platform requires or gives the ability to remap the memory at the address 0x0.
147 This function can do nothing if this feature is not relevant to your platform.
151 ArmPlatformBootRemapping (
157 if (FeaturePcdGet(PcdNorFlashRemapping
)) {
158 SerialPrint ("Secure ROM at 0x0\n\r");
160 Value
= MmioRead32(ARM_VE_SYS_CFGRW1_REG
); //Scc - CFGRW1
161 // Remap the DRAM to 0x0
162 MmioWrite32(ARM_VE_SYS_CFGRW1_REG
, (Value
& 0x0FFFFFFF) | ARM_VE_CFGRW1_REMAP_DRAM
);
167 Initialize controllers that must setup in the normal world
169 This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
174 ArmPlatformNormalInitialize (
178 // Configure periodic timer (TIMER0) for 1MHz operation
179 MmioOr32 (SP810_CTRL_BASE
+ SP810_SYS_CTRL_REG
, SP810_SYS_CTRL_TIMER0_TIMCLK
);
180 // Configure 1MHz clock
181 MmioOr32 (SP810_CTRL_BASE
+ SP810_SYS_CTRL_REG
, SP810_SYS_CTRL_TIMER1_TIMCLK
);
182 // configure SP810 to use 1MHz clock and disable
183 MmioAndThenOr32 (SP810_CTRL_BASE
+ SP810_SYS_CTRL_REG
, ~SP810_SYS_CTRL_TIMER2_EN
, SP810_SYS_CTRL_TIMER2_TIMCLK
);
184 // Configure SP810 to use 1MHz clock and disable
185 MmioAndThenOr32 (SP810_CTRL_BASE
+ SP810_SYS_CTRL_REG
, ~SP810_SYS_CTRL_TIMER3_EN
, SP810_SYS_CTRL_TIMER3_TIMCLK
);
189 Initialize the system (or sometimes called permanent) memory
191 This memory is generally represented by the DRAM.
195 ArmPlatformInitializeSystemMemory (
199 PL341DmcInit(ARM_VE_DMC_BASE
, &DDRTimings
);
200 PL301AxiInit(ARM_VE_FAXI_BASE
);
204 PrePeiCoreGetMpCoreInfo (
205 OUT UINTN
*CoreCount
,
206 OUT ARM_CORE_INFO
**ArmCoreTable
209 *CoreCount
= sizeof(mVersatileExpressMpCoreInfoCTA9x4
) / sizeof(ARM_CORE_INFO
);
210 *ArmCoreTable
= mVersatileExpressMpCoreInfoCTA9x4
;
215 // Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore
216 EFI_GUID mArmMpCoreInfoPpiGuid
= ARM_MP_CORE_INFO_PPI_GUID
;
217 ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi
= { PrePeiCoreGetMpCoreInfo
};
219 EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable
[] = {
221 EFI_PEI_PPI_DESCRIPTOR_PPI
,
222 &mArmMpCoreInfoPpiGuid
,
228 ArmPlatformGetPlatformPpiList (
229 OUT UINTN
*PpiListSize
,
230 OUT EFI_PEI_PPI_DESCRIPTOR
**PpiList
233 *PpiListSize
= sizeof(gPlatformPpiTable
);
234 *PpiList
= gPlatformPpiTable
;