ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/CTA9x4.c

   1 /** @file
   2 *
   3 *  Copyright (c) 2011, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #include <Library/IoLib.h>
  16 #include <Library/ArmTrustZoneLib.h>
  17 #include <Library/ArmPlatformLib.h>
  18 #include <Library/DebugLib.h>
  19 #include <Library/PcdLib.h>
  20 #include <Library/SerialPortLib.h>
  21
  22 #include <Drivers/PL341Dmc.h>
  23 #include <Drivers/PL301Axi.h>
  24 #include <Drivers/PL310L2Cache.h>
  25 #include <Drivers/SP804Timer.h>
  26
  27 #define SerialPrint(txt)  SerialPortWrite (txt, AsciiStrLen(txt)+1);
  28
  29 // DDR2 timings
  30 PL341_DMC_CONFIG DDRTimings = {
  31   .base   = ARM_VE_DMC_BASE,
  32   .phy_ctrl_base  = 0x0,  //There is no DDR2 PHY controller on CTA9 test chip
  33   .MaxChip   = 1,
  34   .IsUserCfg = TRUE,
  35   .User0Cfg = 0x7C924924,
  36   .User2Cfg = (TC_UIOLHXC_VALUE << TC_UIOLHNC_SHIFT) | (TC_UIOLHXC_VALUE << TC_UIOLHPC_SHIFT) | (0x1 << TC_UIOHOCT_SHIFT) | (0x1 << TC_UIOHSTOP_SHIFT),
  37   .HasQos    = TRUE,
  38   .refresh_prd  = 0x3D0,
  39   .cas_latency  = 0x8,
  40   .write_latency  = 0x3,
  41   .t_mrd    = 0x2,
  42   .t_ras    = 0xA,
  43   .t_rc   = 0xE,
  44   .t_rcd    = 0x104,
  45   .t_rfc    = 0x2f32,
  46   .t_rp   = 0x14,
  47   .t_rrd    = 0x2,
  48   .t_wr   = 0x4,
  49   .t_wtr    = 0x2,
  50   .t_xp   = 0x2,
  51   .t_xsr    = 0xC8,
  52   .t_esr    = 0x14,
  53   .MemoryCfg   = DMC_MEMORY_CONFIG_ACTIVE_CHIP_1 | DMC_MEMORY_CONFIG_BURST_4 |
  54                         DMC_MEMORY_CONFIG_ROW_ADDRESS_15 | DMC_MEMORY_CONFIG_COLUMN_ADDRESS_10,
  55   .MemoryCfg2  = DMC_MEMORY_CFG2_DQM_INIT | DMC_MEMORY_CFG2_CKE_INIT |
  56             DMC_MEMORY_CFG2_BANK_BITS_3 | DMC_MEMORY_CFG2_MEM_WIDTH_32,
  57   .MemoryCfg3  = 0x00000001,
  58   .ChipCfg0    = 0x00010000,
  59   .t_faw    = 0x00000A0D,
  60   .ModeReg = DDR2_MR_BURST_LENGTH_4 | DDR2_MR_CAS_LATENCY_4 | DDR2_MR_WR_CYCLES_4,
  61   .ExtModeReg = DDR_EMR_RTT_50R | (DDR_EMR_ODS_VAL << DDR_EMR_ODS_MASK),
  62 };
  63
  64 /**
  65   Return if Trustzone is supported by your platform
  66
  67   A non-zero value must be returned if you want to support a Secure World on your platform.
  68   ArmVExpressTrustzoneInit() will later set up the secure regions.
  69   This function can return 0 even if Trustzone is supported by your processor. In this case,
  70   the platform will continue to run in Secure World.
  71
  72   @return   A non-zero value if Trustzone supported.
  73
  74 **/
  75 UINTN
  76 ArmPlatformTrustzoneSupported (
  77   VOID
  78   )
  79 {
  80   return (MmioRead32(ARM_VE_SYS_CFGRW1_REG) & ARM_VE_CFGRW1_TZASC_EN_BIT_MASK);
  81 }
  82
  83 /**
  84   Initialize the Secure peripherals and memory regions
  85
  86   If Trustzone is supported by your platform then this function makes the required initialization
  87   of the secure peripherals and memory regions.
  88
  89 **/
  90 VOID ArmPlatformTrustzoneInit(VOID) {
  91     //
  92     // Setup TZ Protection Controller
  93     //
  94
  95     // Set Non Secure access for all devices
  96     TZPCSetDecProtBits(ARM_VE_TZPC_BASE, TZPC_DECPROT_0, 0xFFFFFFFF);
  97     TZPCSetDecProtBits(ARM_VE_TZPC_BASE, TZPC_DECPROT_1, 0xFFFFFFFF);
  98     TZPCSetDecProtBits(ARM_VE_TZPC_BASE, TZPC_DECPROT_2, 0xFFFFFFFF);
  99
 100     // Remove Non secure access to secure devices
 101     TZPCClearDecProtBits(ARM_VE_TZPC_BASE, TZPC_DECPROT_0,
 102          ARM_VE_DECPROT_BIT_TZPC | ARM_VE_DECPROT_BIT_DMC_TZASC | ARM_VE_DECPROT_BIT_NMC_TZASC | ARM_VE_DECPROT_BIT_SMC_TZASC);
 103
 104     TZPCClearDecProtBits(ARM_VE_TZPC_BASE, TZPC_DECPROT_2,
 105          ARM_VE_DECPROT_BIT_EXT_MAST_TZ | ARM_VE_DECPROT_BIT_DMC_TZASC_LOCK | ARM_VE_DECPROT_BIT_NMC_TZASC_LOCK | ARM_VE_DECPROT_BIT_SMC_TZASC_LOCK);
 106
 107
 108     //
 109     // Setup TZ Address Space Controller for the SMC. Create 5 Non Secure regions (NOR0, NOR1, SRAM, SMC Peripheral regions)
 110     //
 111
 112     // NOR Flash 0 non secure (BootMon)
 113     TZASCSetRegion(ARM_VE_TZASC_BASE,1,TZASC_REGION_ENABLED,
 114         ARM_VE_SMB_NOR0_BASE,0,
 115         TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW);
 116
 117     // NOR Flash 1. The first half of the NOR Flash1 must be secure for the secure firmware (sec_uefi.bin)
 118 #if EDK2_ARMVE_SECURE_SYSTEM
 119     //Note: Your OS Kernel must be aware of the secure regions before to enable this region
 120     TZASCSetRegion(ARM_VE_TZASC_BASE,2,TZASC_REGION_ENABLED,
 121         ARM_VE_SMB_NOR1_BASE + SIZE_32MB,0,
 122         TZASC_REGION_SIZE_32MB, TZASC_REGION_SECURITY_NSRW);
 123 #else
 124     TZASCSetRegion(ARM_VE_TZASC_BASE,2,TZASC_REGION_ENABLED,
 125         ARM_VE_SMB_NOR1_BASE,0,
 126         TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW);
 127 #endif
 128
 129     // Base of SRAM. Only half of SRAM in Non Secure world
 130     // First half non secure (16MB) + Second Half secure (16MB) = 32MB of SRAM
 131 #if EDK2_ARMVE_SECURE_SYSTEM
 132     //Note: Your OS Kernel must be aware of the secure regions before to enable this region
 133     TZASCSetRegion(ARM_VE_TZASC_BASE,3,TZASC_REGION_ENABLED,
 134         ARM_VE_SMB_SRAM_BASE,0,
 135         TZASC_REGION_SIZE_16MB, TZASC_REGION_SECURITY_NSRW);
 136 #else
 137     TZASCSetRegion(ARM_VE_TZASC_BASE,3,TZASC_REGION_ENABLED,
 138         ARM_VE_SMB_SRAM_BASE,0,
 139         TZASC_REGION_SIZE_32MB, TZASC_REGION_SECURITY_NSRW);
 140 #endif
 141
 142     // Memory Mapped Peripherals. All in non secure world
 143     TZASCSetRegion(ARM_VE_TZASC_BASE,4,TZASC_REGION_ENABLED,
 144         ARM_VE_SMB_PERIPH_BASE,0,
 145         TZASC_REGION_SIZE_64MB, TZASC_REGION_SECURITY_NSRW);
 146
 147     // MotherBoard Peripherals and On-chip peripherals.
 148     TZASCSetRegion(ARM_VE_TZASC_BASE,5,TZASC_REGION_ENABLED,
 149         ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE,0,
 150         TZASC_REGION_SIZE_256MB, TZASC_REGION_SECURITY_NSRW);
 151 }
 152
 153 /**
 154   Return the current Boot Mode
 155
 156   This function returns the boot reason on the platform
 157
 158   @return   Return the current Boot Mode of the platform
 159
 160 **/
 161 EFI_BOOT_MODE
 162 ArmPlatformGetBootMode (
 163   VOID
 164   )
 165 {
 166   return BOOT_WITH_FULL_CONFIGURATION;
 167 }
 168
 169 /**
 170   Remap the memory at 0x0
 171
 172   Some platform requires or gives the ability to remap the memory at the address 0x0.
 173   This function can do nothing if this feature is not relevant to your platform.
 174
 175 **/
 176 VOID
 177 ArmPlatformBootRemapping (
 178   VOID
 179   )
 180 {
 181   UINT32 Value;
 182
 183   if (FeaturePcdGet(PcdNorFlashRemapping)) {
 184     SerialPrint ("Secure ROM at 0x0\n\r");
 185   } else {
 186     Value = MmioRead32(ARM_VE_SYS_CFGRW1_REG); //Scc - CFGRW1
 187     // Remap the DRAM to 0x0
 188     MmioWrite32(ARM_VE_SYS_CFGRW1_REG, (Value & 0x0FFFFFFF) | ARM_VE_CFGRW1_REMAP_DRAM);
 189   }
 190
 191 /**
 192   Initialize controllers that must setup at the early stage
 193
 194   Some peripherals must be initialized in Secure World.
 195   For example, some L2x0 requires to be initialized in Secure World
 196
 197 **/
 198 VOID
 199 ArmPlatformSecInitialize (
 200   VOID
 201   ) {
 202   // The L2x0 controller must be intialize in Secure World
 203   L2x0CacheInit(PcdGet32(PcdL2x0ControllerBase),
 204       PL310_TAG_LATENCIES(L2x0_LATENCY_8_CYCLES,L2x0_LATENCY_8_CYCLES,L2x0_LATENCY_8_CYCLES),
 205       PL310_DATA_LATENCIES(L2x0_LATENCY_8_CYCLES,L2x0_LATENCY_8_CYCLES,L2x0_LATENCY_8_CYCLES),
 206       0,~0, // Use default setting for the Auxiliary Control Register
 207       FALSE);
 208 }
 209
 210 /**
 211   Initialize controllers that must setup in the normal world
 212
 213   This function is called by the ArmPlatformPkg/Pei or ArmPlatformPkg/Pei/PlatformPeim
 214   in the PEI phase.
 215
 216 **/
 217 VOID
 218 ArmPlatformNormalInitialize (
 219   VOID
 220   )
 221 {
 222   // Configure periodic timer (TIMER0) for 1MHz operation
 223   MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER0_TIMCLK);
 224   // Configure 1MHz clock
 225   MmioOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, SP810_SYS_CTRL_TIMER1_TIMCLK);
 226   // configure SP810 to use 1MHz clock and disable
 227   MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER2_EN, SP810_SYS_CTRL_TIMER2_TIMCLK);
 228   // Configure SP810 to use 1MHz clock and disable
 229   MmioAndThenOr32 (SP810_CTRL_BASE + SP810_SYS_CTRL_REG, ~SP810_SYS_CTRL_TIMER3_EN, SP810_SYS_CTRL_TIMER3_TIMCLK);
 230 }
 231
 232 /**
 233   Initialize the system (or sometimes called permanent) memory
 234
 235   This memory is generally represented by the DRAM.
 236
 237 **/
 238 VOID
 239 ArmPlatformInitializeSystemMemory (
 240   VOID
 241   )
 242 {
 243   PL341DmcInit(&DDRTimings);
 244   PL301AxiInit(ARM_VE_FAXI_BASE);
 245 }