ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/Arm/RTSMHelper.asm

   1 //
   2 //  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
   3 //
   4 //  This program and the accompanying materials
   5 //  are licensed and made available under the terms and conditions of the BSD License
   6 //  which accompanies this distribution.  The full text of the license may be found at
   7 //  http://opensource.org/licenses/bsd-license.php
   8 //
   9 //  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 //  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11 //
  12 //
  13
  14 #include <AsmMacroIoLib.h>
  15 #include <Base.h>
  16 #include <Library/PcdLib.h>
  17
  18 #include <Chipset/ArmCortexA9.h>
  19
  20 #include <AutoGen.h>
  21
  22   INCLUDE AsmMacroIoLib.inc
  23
  24   EXPORT    ArmGetCpuCountPerCluster
  25   EXPORT    ArmPlatformIsPrimaryCore
  26
  27   IMPORT  _gPcd_FixedAtBuild_PcdArmPrimaryCore
  28   IMPORT  _gPcd_FixedAtBuild_PcdArmPrimaryCoreMask
  29
  30   AREA RTSMHelper, CODE, READONLY
  31
  32 // IN None
  33 // OUT r0 = SCU Base Address
  34 ArmGetScuBaseAddress FUNCTION
  35   // Read Configuration Base Address Register. ArmCBar cannot be called to get
  36   // the Configuration BAR as a stack is not necessary setup. The SCU is at the
  37   // offset 0x0000 from the Private Memory Region.
  38   mrc   p15, 4, r0, c15, c0, 0
  39   bx  lr
  40   ENDFUNC
  41
  42 // IN None
  43 // OUT r0 = number of cores present in the system
  44 ArmGetCpuCountPerCluster FUNCTION
  45   stmfd SP!, {r1-r2}
  46
  47   // Read CP15 MIDR
  48   mrc   p15, 0, r1, c0, c0, 0
  49
  50   // Check if the CPU is A15
  51   mov   r1, r1, LSR #4
  52   mov   r0, #ARM_CPU_TYPE_MASK
  53   and   r1, r1, r0
  54
  55   mov   r0, #ARM_CPU_TYPE_A15
  56   cmp   r1, r0
  57   beq   _Read_cp15_reg
  58
  59 _CPU_is_not_A15
  60   mov   r2, lr                              ; Save link register
  61   bl    ArmGetScuBaseAddress                ; Read SCU Base Address
  62   mov   lr, r2                              ; Restore link register val
  63   ldr   r0, [r0, #A9_SCU_CONFIG_OFFSET]     ; Read SCU Config reg to get CPU count
  64   b     _Return
  65
  66 _Read_cp15_reg
  67   mrc   p15, 1, r0, c9, c0, 2            ; Read C9 register of CP15 to get CPU count
  68   lsr   r0, #24
  69
  70
  71 _Return
  72   and   r0, r0, #3
  73   // Add '1' to the number of CPU on the Cluster
  74   add   r0, r0, #1
  75   ldmfd SP!, {r1-r2}
  76   bx lr
  77   ENDFUNC
  78
  79 //UINTN
  80 //ArmPlatformIsPrimaryCore (
  81 //  IN UINTN MpId
  82 //  );
  83 ArmPlatformIsPrimaryCore FUNCTION
  84   LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCoreMask, r1)
  85   ldr   r1, [r1]
  86   and   r0, r0, r1
  87   LoadConstantToReg (_gPcd_FixedAtBuild_PcdArmPrimaryCore, r1)
  88   ldr   r1, [r1]
  89   cmp   r0, r1
  90   moveq r0, #1
  91   movne r0, #0
  92   bx    lr
  93   ENDFUNC
  94
  95   END