ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c

   1 /** @file
   2 *
   3 *  Copyright (c) 2011-2014, ARM Limited. All rights reserved.
   4 *
   5 *  This program and the accompanying materials
   6 *  are licensed and made available under the terms and conditions of the BSD License
   7 *  which accompanies this distribution.  The full text of the license may be found at
   8 *  http://opensource.org/licenses/bsd-license.php
   9 *
  10 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  11 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  12 *
  13 **/
  14
  15 #include <Library/ArmPlatformLib.h>
  16 #include <Library/DebugLib.h>
  17 #include <Library/HobLib.h>
  18 #include <Library/PcdLib.h>
  19 #include <Library/IoLib.h>
  20 #include <Library/MemoryAllocationLib.h>
  21 #include <ArmPlatform.h>
  22
  23 // Number of Virtual Memory Map Descriptors
  24 #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS          6
  25
  26 // DDR attributes
  27 #define DDR_ATTRIBUTES_CACHED           ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
  28 #define DDR_ATTRIBUTES_UNCACHED         ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
  29
  30 /**
  31   Return the Virtual Memory Map of your platform
  32
  33   This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
  34
  35   @param[out]   VirtualMemoryMap    Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
  36                                     Virtual Memory mapping. This array must be ended by a zero-filled
  37                                     entry
  38
  39 **/
  40 VOID
  41 ArmPlatformGetVirtualMemoryMap (
  42   IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
  43   )
  44 {
  45   ARM_MEMORY_REGION_ATTRIBUTES  CacheAttributes;
  46   EFI_RESOURCE_ATTRIBUTE_TYPE   ResourceAttributes;
  47   UINTN                         Index = 0;
  48   ARM_MEMORY_REGION_DESCRIPTOR  *VirtualMemoryTable;
  49   UINT32                        SysId;
  50   BOOLEAN                       HasSparseMemory;
  51   EFI_VIRTUAL_ADDRESS           SparseMemoryBase;
  52   UINT64                        SparseMemorySize;
  53
  54   ASSERT (VirtualMemoryMap != NULL);
  55
  56   // The FVP model has Sparse memory
  57   SysId = MmioRead32 (ARM_VE_SYS_ID_REG);
  58   if (SysId != ARM_RTSM_SYS_ID) {
  59     HasSparseMemory = TRUE;
  60
  61     ResourceAttributes =
  62         EFI_RESOURCE_ATTRIBUTE_PRESENT |
  63         EFI_RESOURCE_ATTRIBUTE_INITIALIZED |
  64         EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |
  65         EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |
  66         EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |
  67         EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |
  68         EFI_RESOURCE_ATTRIBUTE_TESTED;
  69
  70     // Declared the additional DRAM from 2GB to 4GB
  71     SparseMemoryBase = 0x0880000000;
  72     SparseMemorySize = SIZE_2GB;
  73
  74     BuildResourceDescriptorHob (
  75         EFI_RESOURCE_SYSTEM_MEMORY,
  76         ResourceAttributes,
  77         SparseMemoryBase,
  78         SparseMemorySize);
  79   } else {
  80     HasSparseMemory = FALSE;
  81     SparseMemoryBase = 0x0;
  82     SparseMemorySize = 0x0;
  83   }
  84
  85   VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
  86   if (VirtualMemoryTable == NULL) {
  87       return;
  88   }
  89
  90   if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
  91       CacheAttributes = DDR_ATTRIBUTES_CACHED;
  92   } else {
  93       CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
  94   }
  95
  96   // ReMap (Either NOR Flash or DRAM)
  97   VirtualMemoryTable[Index].PhysicalBase = ARM_VE_REMAP_BASE;
  98   VirtualMemoryTable[Index].VirtualBase  = ARM_VE_REMAP_BASE;
  99   VirtualMemoryTable[Index].Length       = ARM_VE_REMAP_SZ;
 100
 101   if (FeaturePcdGet(PcdNorFlashRemapping) == FALSE) {
 102     // Map the NOR Flash as Secure Memory
 103     if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
 104       VirtualMemoryTable[Index].Attributes   = DDR_ATTRIBUTES_CACHED;
 105     } else {
 106       VirtualMemoryTable[Index].Attributes   = DDR_ATTRIBUTES_UNCACHED;
 107     }
 108   } else {
 109     // DRAM mapping
 110     VirtualMemoryTable[Index].Attributes   = CacheAttributes;
 111   }
 112
 113   // DDR
 114   VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_DRAM_BASE;
 115   VirtualMemoryTable[Index].VirtualBase  = ARM_VE_DRAM_BASE;
 116   VirtualMemoryTable[Index].Length       = ARM_VE_DRAM_SZ;
 117   VirtualMemoryTable[Index].Attributes   = CacheAttributes;
 118
 119   // CPU peripherals. TRM. Manual says not all of them are implemented.
 120   VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_ON_CHIP_PERIPH_BASE;
 121   VirtualMemoryTable[Index].VirtualBase  = ARM_VE_ON_CHIP_PERIPH_BASE;
 122   VirtualMemoryTable[Index].Length       = ARM_VE_ON_CHIP_PERIPH_SZ;
 123   VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
 124
 125   // SMB CS0-CS1 - NOR Flash 1 & 2
 126   VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE;
 127   VirtualMemoryTable[Index].VirtualBase  = ARM_VE_SMB_NOR0_BASE;
 128   VirtualMemoryTable[Index].Length       = ARM_VE_SMB_NOR0_SZ + ARM_VE_SMB_NOR1_SZ;
 129   VirtualMemoryTable[Index].Attributes   = CacheAttributes;
 130
 131   // SMB CS2 - SRAM
 132   VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_SRAM_BASE;
 133   VirtualMemoryTable[Index].VirtualBase  = ARM_VE_SMB_SRAM_BASE;
 134   VirtualMemoryTable[Index].Length       = ARM_VE_SMB_SRAM_SZ;
 135   VirtualMemoryTable[Index].Attributes   = CacheAttributes;
 136
 137   // Peripheral CS2 and CS3
 138   VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE;
 139   VirtualMemoryTable[Index].VirtualBase  = ARM_VE_SMB_PERIPH_BASE;
 140   VirtualMemoryTable[Index].Length       = 2 * ARM_VE_SMB_PERIPH_SZ;
 141   VirtualMemoryTable[Index].Attributes   = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
 142
 143   // Map sparse memory region if present
 144   if (HasSparseMemory) {
 145     VirtualMemoryTable[++Index].PhysicalBase = SparseMemoryBase;
 146     VirtualMemoryTable[Index].VirtualBase    = SparseMemoryBase;
 147     VirtualMemoryTable[Index].Length         = SparseMemorySize;
 148     VirtualMemoryTable[Index].Attributes     = CacheAttributes;
 149   }
 150
 151   // End of Table
 152   VirtualMemoryTable[++Index].PhysicalBase = 0;
 153   VirtualMemoryTable[Index].VirtualBase  = 0;
 154   VirtualMemoryTable[Index].Length       = 0;
 155   VirtualMemoryTable[Index].Attributes   = (ARM_MEMORY_REGION_ATTRIBUTES)0;
 156
 157   *VirtualMemoryMap = VirtualMemoryTable;
 158 }