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1 /** @file
2 *
3 * Copyright (c) 2011, ARM Limited. All rights reserved.
4 *
5 * This program and the accompanying materials
6 * are licensed and made available under the terms and conditions of the BSD License
7 * which accompanies this distribution. The full text of the license may be found at
8 * http://opensource.org/licenses/bsd-license.php
9 *
10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12 *
13 **/
14
15 #include <Library/ArmPlatformLib.h>
16 #include <Library/DebugLib.h>
17 #include <Library/PcdLib.h>
18 #include <Library/IoLib.h>
19 #include <Library/MemoryAllocationLib.h>
20 #include <ArmPlatform.h>
21
22 // Number of Virtual Memory Map Descriptors without a Logic Tile
23 #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 5
24
25 // DDR attributes
26 #define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
27 #define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
28
29 /**
30 Return the Virtual Memory Map of your platform
31
32 This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
33
34 @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
35 Virtual Memory mapping. This array must be ended by a zero-filled
36 entry
37
38 **/
39 VOID
40 ArmPlatformGetVirtualMemoryMap (
41 IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
42 )
43 {
44 ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes;
45 UINTN Index = 0;
46 ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
47
48 ASSERT(VirtualMemoryMap != NULL);
49
50 VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
51 if (VirtualMemoryTable == NULL) {
52 return;
53 }
54
55 if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
56 CacheAttributes = DDR_ATTRIBUTES_CACHED;
57 } else {
58 CacheAttributes = DDR_ATTRIBUTES_UNCACHED;
59 }
60
61 // ReMap (Either NOR Flash or DRAM)
62 VirtualMemoryTable[Index].PhysicalBase = ARM_VE_REMAP_BASE;
63 VirtualMemoryTable[Index].VirtualBase = ARM_VE_REMAP_BASE;
64 VirtualMemoryTable[Index].Length = ARM_VE_REMAP_SZ;
65
66 if (FeaturePcdGet(PcdNorFlashRemapping) == FALSE) {
67 // Map the NOR Flash as Secure Memory
68 if (FeaturePcdGet(PcdCacheEnable) == TRUE) {
69 VirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_CACHED;
70 } else {
71 VirtualMemoryTable[Index].Attributes = DDR_ATTRIBUTES_UNCACHED;
72 }
73 } else {
74 // DRAM mapping
75 VirtualMemoryTable[Index].Attributes = CacheAttributes;
76 }
77
78 // DDR
79 VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_DRAM_BASE;
80 VirtualMemoryTable[Index].VirtualBase = ARM_VE_DRAM_BASE;
81 VirtualMemoryTable[Index].Length = ARM_VE_DRAM_SZ;
82 VirtualMemoryTable[Index].Attributes = CacheAttributes;
83
84 // CPU peripherals. TRM. Manual says not all of them are implemented.
85 VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_ON_CHIP_PERIPH_BASE;
86 VirtualMemoryTable[Index].VirtualBase = ARM_VE_ON_CHIP_PERIPH_BASE;
87 VirtualMemoryTable[Index].Length = ARM_VE_ON_CHIP_PERIPH_SZ;
88 VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
89
90 // SMB CS0-CS1 - NOR Flash 1 & 2
91 VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE;
92 VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE;
93 VirtualMemoryTable[Index].Length = ARM_VE_SMB_NOR0_SZ + ARM_VE_SMB_NOR1_SZ;
94 VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
95
96 // SMB CS2 - SRAM
97 VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_SRAM_BASE;
98 VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_SRAM_BASE;
99 VirtualMemoryTable[Index].Length = ARM_VE_SMB_SRAM_SZ;
100 VirtualMemoryTable[Index].Attributes = CacheAttributes;
101
102 // Peripheral CS2 and CS3
103 VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE;
104 VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_PERIPH_BASE;
105 VirtualMemoryTable[Index].Length = 2 * ARM_VE_SMB_PERIPH_SZ;
106 VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
107
108 //TODO:This should be enabled for final release. Right now, ARM VE RTSM crashes.
109 // // If a Logic Tile is connected to The ARM Versatile Express Motherboard
110 // if (MmioRead32(ARM_VE_SYS_PROCID1_REG) != 0) {
111 // VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_EXT_AXI_BASE;
112 // VirtualMemoryTable[Index].VirtualBase = ARM_VE_EXT_AXI_BASE;
113 // VirtualMemoryTable[Index].Length = ARM_VE_EXT_AXI_SZ;
114 // VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
115 //
116 // ASSERT((Index + 1) == (MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS + 1));
117 // } else {
118 // ASSERT((Index + 1) == MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
119 // }
120
121 // End of Table
122 VirtualMemoryTable[++Index].PhysicalBase = 0;
123 VirtualMemoryTable[Index].VirtualBase = 0;
124 VirtualMemoryTable[Index].Length = 0;
125 VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
126
127 *VirtualMemoryMap = VirtualMemoryTable;
128 }
129
130 /**
131 Return the EFI Memory Map provided by extension memory on your platform
132
133 This EFI Memory Map of the System Memory is used by MemoryInitPei module to create the Resource
134 Descriptor HOBs used by DXE core.
135 TODO: CompleteMe .... say this is the memory not covered by the System Memory PCDs
136
137 @param[out] EfiMemoryMap Array of ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR describing an
138 EFI Memory region. This array must be ended by a zero-filled entry
139
140 **/
141 EFI_STATUS
142 ArmPlatformGetAdditionalSystemMemory (
143 OUT ARM_SYSTEM_MEMORY_REGION_DESCRIPTOR** EfiMemoryMap
144 )
145 {
146 return EFI_UNSUPPORTED;
147 }