ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/AArch64/GicV3.S

   1 //
   2 //  Copyright (c) 2013-2014, ARM Limited. All rights reserved.
   3 //
   4 //  This program and the accompanying materials
   5 //  are licensed and made available under the terms and conditions of the BSD License
   6 //  which accompanies this distribution.  The full text of the license may be found at
   7 //  http://opensource.org/licenses/bsd-license.php
   8 //
   9 //  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 //  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11 //
  12 //
  13
  14 #include <AsmMacroIoLibV8.h>
  15 #include <Chipset/AArch64.h>
  16
  17 #ifndef __clang__
  18 // Register definitions used by GCC for GICv3 access.
  19 // These are defined by ARMCC, so keep them in the GCC specific code for now.
  20 #define ICC_SRE_EL2     S3_4_C12_C9_5
  21 #define ICC_SRE_EL3     S3_6_C12_C12_5
  22 #define ICC_CTLR_EL1    S3_0_C12_C12_4
  23 #define ICC_CTLR_EL3    S3_6_C12_C12_4
  24 #define ICC_PMR_EL1     S3_0_C4_C6_0
  25 #endif
  26
  27 .text
  28 .align 3
  29
  30 GCC_ASM_EXPORT(InitializeGicV3)
  31
  32 /* Initialize GICv3 to expose it as a GICv2 as UEFI does not support GICv3 yet */
  33 ASM_PFX(InitializeGicV3):
  34   // We have a GICv3. UEFI still uses the GICv2 mode. We must do enough setup
  35   // to allow Linux to use GICv3 if it chooses.
  36
  37   // In order to setup NS side we need to enable it first.
  38   mrs     x0, scr_el3
  39   orr     x0, x0, #1
  40   msr     scr_el3, x0
  41
  42   // Enable SRE at EL3 and ICC_SRE_EL2 access
  43   mov     x0, #((1 << 3) | (1 << 0))      // Enable | SRE
  44   mrs     x1, ICC_SRE_EL3
  45   orr     x1, x1, x0
  46   msr     ICC_SRE_EL3, x1
  47   isb
  48
  49   // Enable SRE at EL2 and ICC_SRE_EL1 access..
  50   mrs     x1, ICC_SRE_EL2
  51   orr     x1, x1, x0
  52   msr     ICC_SRE_EL2, x1
  53   isb
  54
  55   // Configure CPU interface
  56   msr     ICC_CTLR_EL3, xzr
  57   isb
  58   msr     ICC_CTLR_EL1, xzr
  59   isb
  60
  61   // The MemoryMap view and Register view may not be consistent, So Set PMR again.
  62   mov     w1, #1 << 7                        // allow NS access to GICC_PMR
  63   msr     ICC_PMR_EL1, x1
  64   isb
  65
  66   // Remove the SCR.NS bit
  67   mrs     x0, scr_el3
  68   and     x0, x0, #~SCR_NS
  69   msr     scr_el3, x0
  70   ret