ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/AArch64/GicV3.S

   1 //
   2 //  Copyright (c) 2013-2014, ARM Limited. All rights reserved.
   3 //
   4 //  This program and the accompanying materials
   5 //  are licensed and made available under the terms and conditions of the BSD License
   6 //  which accompanies this distribution.  The full text of the license may be found at
   7 //  http://opensource.org/licenses/bsd-license.php
   8 //
   9 //  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  10 //  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  11 //
  12 //
  13
  14 #include <AsmMacroIoLibV8.h>
  15
  16 // Register definitions used by GCC for GICv3 access.
  17 // These are defined by ARMCC, so keep them in the GCC specific code for now.
  18 #define ICC_SRE_EL2     S3_4_C12_C9_5
  19 #define ICC_SRE_EL3     S3_6_C12_C12_5
  20 #define ICC_CTLR_EL1    S3_0_C12_C12_4
  21 #define ICC_CTLR_EL3    S3_6_C12_C12_4
  22 #define ICC_PMR_EL1     S3_0_C4_C6_0
  23
  24 .text
  25 .align 3
  26
  27 GCC_ASM_EXPORT(InitializeGicV3)
  28
  29 /* Initialize GICv3 to expose it as a GICv2 as UEFI does not support GICv3 yet */
  30 ASM_PFX(InitializeGicV3):
  31   // We have a GICv3. UEFI still uses the GICv2 mode. We must do enough setup
  32   // to allow Linux to use GICv3 if it chooses.
  33
  34   // In order to setup NS side we need to enable it first.
  35   mrs     x0, scr_el3
  36   orr     x0, x0, #1
  37   msr     scr_el3, x0
  38
  39   // Enable SRE at EL3 and ICC_SRE_EL2 access
  40   mov     x0, #((1 << 3) | (1 << 0))      // Enable | SRE
  41   mrs     x1, ICC_SRE_EL3
  42   orr     x1, x1, x0
  43   msr     ICC_SRE_EL3, x1
  44   isb
  45
  46   // Enable SRE at EL2 and ICC_SRE_EL1 access..
  47   mrs     x1, ICC_SRE_EL2
  48   orr     x1, x1, x0
  49   msr     ICC_SRE_EL2, x1
  50   isb
  51
  52   // Configure CPU interface
  53   msr     ICC_CTLR_EL3, xzr
  54   isb
  55   msr     ICC_CTLR_EL1, xzr
  56   isb
  57
  58   // The MemoryMap view and Register view may not be consistent, So Set PMR again.
  59   mov     w1, #1 << 7                        // allow NS access to GICC_PMR
  60   msr     ICC_PMR_EL1, x1
  61   isb
  62
  63   // Remove the SCR.NS bit
  64   mrs     x0, scr_el3
  65   bic     x0, x0, #1
  66   msr     scr_el3, x0
  67   ret