ArmPlatformPkg/ArmVExpressSecLibRTSM: Only use extended name of system registers...
[mirror_edk2.git] / ArmPlatformPkg / ArmVExpressPkg / Library / ArmVExpressSecLibRTSM / AArch64 / GicV3.S
1 //
2 // Copyright (c) 2013-2014, ARM Limited. All rights reserved.
3 //
4 // This program and the accompanying materials
5 // are licensed and made available under the terms and conditions of the BSD License
6 // which accompanies this distribution. The full text of the license may be found at
7 // http://opensource.org/licenses/bsd-license.php
8 //
9 // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
11 //
12 //
13
14 #include <AsmMacroIoLibV8.h>
15
16 #ifndef __clang__
17 // Register definitions used by GCC for GICv3 access.
18 // These are defined by ARMCC, so keep them in the GCC specific code for now.
19 #define ICC_SRE_EL2 S3_4_C12_C9_5
20 #define ICC_SRE_EL3 S3_6_C12_C12_5
21 #define ICC_CTLR_EL1 S3_0_C12_C12_4
22 #define ICC_CTLR_EL3 S3_6_C12_C12_4
23 #define ICC_PMR_EL1 S3_0_C4_C6_0
24 #endif
25
26 .text
27 .align 3
28
29 GCC_ASM_EXPORT(InitializeGicV3)
30
31 /* Initialize GICv3 to expose it as a GICv2 as UEFI does not support GICv3 yet */
32 ASM_PFX(InitializeGicV3):
33 // We have a GICv3. UEFI still uses the GICv2 mode. We must do enough setup
34 // to allow Linux to use GICv3 if it chooses.
35
36 // In order to setup NS side we need to enable it first.
37 mrs x0, scr_el3
38 orr x0, x0, #1
39 msr scr_el3, x0
40
41 // Enable SRE at EL3 and ICC_SRE_EL2 access
42 mov x0, #((1 << 3) | (1 << 0)) // Enable | SRE
43 mrs x1, ICC_SRE_EL3
44 orr x1, x1, x0
45 msr ICC_SRE_EL3, x1
46 isb
47
48 // Enable SRE at EL2 and ICC_SRE_EL1 access..
49 mrs x1, ICC_SRE_EL2
50 orr x1, x1, x0
51 msr ICC_SRE_EL2, x1
52 isb
53
54 // Configure CPU interface
55 msr ICC_CTLR_EL3, xzr
56 isb
57 msr ICC_CTLR_EL1, xzr
58 isb
59
60 // The MemoryMap view and Register view may not be consistent, So Set PMR again.
61 mov w1, #1 << 7 // allow NS access to GICC_PMR
62 msr ICC_PMR_EL1, x1
63 isb
64
65 // Remove the SCR.NS bit
66 mrs x0, scr_el3
67 bic x0, x0, #1
68 msr scr_el3, x0
69 ret