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1 /** @file NorFlashDxe.h
2
3 Copyright (c) 2010, ARM Ltd. All rights reserved.<BR>
4 This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
8
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
11
12 **/
13
14 #ifndef __NOR_FLASH_DXE_H__
15 #define __NOR_FLASH_DXE_H__
16
17
18 #include <Base.h>
19 #include <PiDxe.h>
20
21 #include <Protocol/BlockIo.h>
22 #include <Protocol/FirmwareVolumeBlock.h>
23
24 #include <ArmPlatform.h>
25
26 #define HIGH_16_BITS 0xFFFF0000
27 #define LOW_16_BITS 0x0000FFFF
28 #define LOW_8_BITS 0x000000FF
29
30 // Hardware addresses
31
32 #define VE_SYSTEM_REGISTERS_OFFSET 0x00000000
33 #define SYSTEM_REGISTER_SYS_FLASH 0x0000004C
34
35 #define VE_REGISTER_SYS_FLASH_ADDR ( ARM_VE_BOARD_PERIPH_BASE + VE_SYSTEM_REGISTERS_OFFSET + SYSTEM_REGISTER_SYS_FLASH )
36
37 // Device access macros
38 // These are necessary because we use 2 x 16bit parts to make up 32bit data
39
40 #define FOLD_32BIT_INTO_16BIT(value) ( ( value >> 16 ) | ( value & LOW_16_BITS ) )
41
42 #define GET_LOW_BYTE(value) ( value & LOW_8_BITS )
43 #define GET_HIGH_BYTE(value) ( GET_LOW_BYTE( value >> 16 ) )
44
45 // Each command must be sent simultaneously to both chips,
46 // i.e. at the lower 16 bits AND at the higher 16 bits
47 #define CREATE_NOR_ADDRESS(BaseAddr,OffsetAddr) ( (volatile UINTN *)((BaseAddr) + ((OffsetAddr) << 2)) )
48 #define CREATE_DUAL_CMD(Cmd) ( ( Cmd << 16) | ( Cmd & LOW_16_BITS) )
49 #define SEND_NOR_COMMAND(BaseAddr,OffsetAddr,Cmd) ( *CREATE_NOR_ADDRESS(BaseAddr,OffsetAddr) = CREATE_DUAL_CMD(Cmd) )
50 #define GET_NOR_BLOCK_ADDRESS(BaseAddr,Lba,LbaSize)( BaseAddr + (UINTN)(Lba * LbaSize) )
51
52 // Status Register Bits
53 #define P30_SR_BIT_WRITE 0x00800080 /* Bit 7 */
54 #define P30_SR_BIT_ERASE_SUSPEND 0x00400040 /* Bit 6 */
55 #define P30_SR_BIT_ERASE 0x00200020 /* Bit 5 */
56 #define P30_SR_BIT_PROGRAM 0x00100010 /* Bit 4 */
57 #define P30_SR_BIT_VPP 0x00080008 /* Bit 3 */
58 #define P30_SR_BIT_PROGRAM_SUSPEND 0x00040004 /* Bit 2 */
59 #define P30_SR_BIT_BLOCK_LOCKED 0x00020002 /* Bit 1 */
60 #define P30_SR_BIT_BEFP 0x00010001 /* Bit 0 */
61
62 // Device Commands for Intel StrataFlash(R) Embedded Memory (P30) Family
63
64 // On chip buffer size for buffered programming operations
65 // There are 2 chips, each chip can buffer up to 32 (16-bit)words, and each word is 2 bytes.
66 // Therefore the total size of the buffer is 2 x 32 x 2 = 128 bytes
67 #define P30_MAX_BUFFER_SIZE_IN_BYTES ((UINTN)128)
68 #define P30_MAX_BUFFER_SIZE_IN_WORDS (P30_MAX_BUFFER_SIZE_IN_BYTES/((UINTN)4))
69 #define MAX_BUFFERED_PROG_ITERATIONS 10000000
70 #define BOUNDARY_OF_32_WORDS 0x7F
71
72 // CFI Addresses
73 #define P30_CFI_ADDR_QUERY_UNIQUE_QRY 0x10
74 #define P30_CFI_ADDR_VENDOR_ID 0x13
75
76 // CFI Data
77 #define CFI_QRY 0x00595251
78
79 // READ Commands
80 #define P30_CMD_READ_DEVICE_ID 0x0090
81 #define P30_CMD_READ_STATUS_REGISTER 0x0070
82 #define P30_CMD_CLEAR_STATUS_REGISTER 0x0050
83 #define P30_CMD_READ_ARRAY 0x00FF
84 #define P30_CMD_READ_CFI_QUERY 0x0098
85
86 // WRITE Commands
87 #define P30_CMD_WORD_PROGRAM_SETUP 0x0040
88 #define P30_CMD_ALTERNATE_WORD_PROGRAM_SETUP 0x0010
89 #define P30_CMD_BUFFERED_PROGRAM_SETUP 0x00E8
90 #define P30_CMD_BUFFERED_PROGRAM_CONFIRM 0x00D0
91 #define P30_CMD_BEFP_SETUP 0x0080
92 #define P30_CMD_BEFP_CONFIRM 0x00D0
93
94 // ERASE Commands
95 #define P30_CMD_BLOCK_ERASE_SETUP 0x0020
96 #define P30_CMD_BLOCK_ERASE_CONFIRM 0x00D0
97
98 // SUSPEND Commands
99 #define P30_CMD_PROGRAM_OR_ERASE_SUSPEND 0x00B0
100 #define P30_CMD_SUSPEND_RESUME 0x00D0
101
102 // BLOCK LOCKING / UNLOCKING Commands
103 #define P30_CMD_LOCK_BLOCK_SETUP 0x0060
104 #define P30_CMD_LOCK_BLOCK 0x0001
105 #define P30_CMD_UNLOCK_BLOCK 0x00D0
106 #define P30_CMD_LOCK_DOWN_BLOCK 0x002F
107
108 // PROTECTION Commands
109 #define P30_CMD_PROGRAM_PROTECTION_REGISTER_SETUP 0x00C0
110
111 // CONFIGURATION Commands
112 #define P30_CMD_READ_CONFIGURATION_REGISTER_SETUP 0x0060
113 #define P30_CMD_READ_CONFIGURATION_REGISTER 0x0003
114
115 #define NOR_FLASH_SIGNATURE SIGNATURE_32('n', 'o', 'r', '0')
116 #define INSTANCE_FROM_FVB_THIS(a) CR(a, NOR_FLASH_INSTANCE, FvbProtocol, NOR_FLASH_SIGNATURE)
117 #define INSTANCE_FROM_BLKIO_THIS(a) CR(a, NOR_FLASH_INSTANCE, BlockIoProtocol, NOR_FLASH_SIGNATURE)
118
119 typedef struct _NOR_FLASH_INSTANCE NOR_FLASH_INSTANCE;
120
121 typedef EFI_STATUS (*NOR_FLASH_INITIALIZE) (NOR_FLASH_INSTANCE* Instance);
122
123 typedef struct {
124 UINTN BaseAddress;
125 UINTN Size;
126 UINTN BlockSize;
127 EFI_GUID Guid;
128 } NOR_FLASH_DESCRIPTION;
129
130 typedef struct {
131 VENDOR_DEVICE_PATH Vendor;
132 EFI_DEVICE_PATH_PROTOCOL End;
133 } NOR_FLASH_DEVICE_PATH;
134
135 struct _NOR_FLASH_INSTANCE {
136 UINT32 Signature;
137 EFI_HANDLE Handle;
138
139 BOOLEAN Initialized;
140 NOR_FLASH_INITIALIZE Initialize;
141
142 UINTN BaseAddress;
143 UINTN Size;
144
145 EFI_BLOCK_IO_PROTOCOL BlockIoProtocol;
146 EFI_BLOCK_IO_MEDIA Media;
147
148 BOOLEAN SupportFvb;
149 EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL FvbProtocol;
150
151 NOR_FLASH_DEVICE_PATH DevicePath;
152 };
153
154 EFI_STATUS
155 EFIAPI
156 NorFlashBlkIoInitialize (
157 IN NOR_FLASH_INSTANCE* Instance
158 );
159
160 EFI_STATUS
161 NorFlashReadCfiData (
162 IN UINTN BaseAddress,
163 IN UINTN CFI_Offset,
164 IN UINT32 NumberOfBytes,
165 OUT UINT32 *Data
166 );
167
168 EFI_STATUS
169 NorFlashWriteBuffer (
170 IN UINTN TargetAddress,
171 IN UINTN BufferSizeInBytes,
172 IN UINT32 *Buffer
173 );
174
175
176 //
177 // BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.Reset
178 //
179 EFI_STATUS
180 EFIAPI
181 NorFlashBlockIoReset (
182 IN EFI_BLOCK_IO_PROTOCOL *This,
183 IN BOOLEAN ExtendedVerification
184 );
185
186 //
187 // BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.ReadBlocks
188 //
189 EFI_STATUS
190 EFIAPI
191 NorFlashBlockIoReadBlocks (
192 IN EFI_BLOCK_IO_PROTOCOL *This,
193 IN UINT32 MediaId,
194 IN EFI_LBA Lba,
195 IN UINTN BufferSizeInBytes,
196 OUT VOID *Buffer
197 );
198
199 //
200 // BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.WriteBlocks
201 //
202 EFI_STATUS
203 EFIAPI
204 NorFlashBlockIoWriteBlocks (
205 IN EFI_BLOCK_IO_PROTOCOL *This,
206 IN UINT32 MediaId,
207 IN EFI_LBA Lba,
208 IN UINTN BufferSizeInBytes,
209 IN VOID *Buffer
210 );
211
212 //
213 // BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.FlushBlocks
214 //
215 EFI_STATUS
216 EFIAPI
217 NorFlashBlockIoFlushBlocks (
218 IN EFI_BLOCK_IO_PROTOCOL *This
219 );
220
221
222 //
223 // NorFlashFvbDxe.c
224 //
225
226 EFI_STATUS
227 EFIAPI
228 NorFlashFvbInitialize (
229 IN NOR_FLASH_INSTANCE* Instance
230 );
231
232 EFI_STATUS
233 EFIAPI
234 FvbGetAttributes(
235 IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
236 OUT EFI_FVB_ATTRIBUTES_2 *Attributes
237 );
238
239 EFI_STATUS
240 EFIAPI
241 FvbSetAttributes(
242 IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
243 IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes
244 );
245
246 EFI_STATUS
247 EFIAPI
248 FvbGetPhysicalAddress(
249 IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
250 OUT EFI_PHYSICAL_ADDRESS *Address
251 );
252
253 EFI_STATUS
254 EFIAPI
255 FvbGetBlockSize(
256 IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
257 IN EFI_LBA Lba,
258 OUT UINTN *BlockSize,
259 OUT UINTN *NumberOfBlocks
260 );
261
262 EFI_STATUS
263 EFIAPI
264 FvbRead(
265 IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
266 IN EFI_LBA Lba,
267 IN UINTN Offset,
268 IN OUT UINTN *NumBytes,
269 IN OUT UINT8 *Buffer
270 );
271
272 EFI_STATUS
273 EFIAPI
274 FvbWrite(
275 IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
276 IN EFI_LBA Lba,
277 IN UINTN Offset,
278 IN OUT UINTN *NumBytes,
279 IN UINT8 *Buffer
280 );
281
282 EFI_STATUS
283 EFIAPI
284 FvbEraseBlocks(
285 IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
286 ...
287 );
288
289 //
290 // NorFlashDxe.c
291 //
292
293 EFI_STATUS
294 NorFlashUnlockAndEraseSingleBlock(
295 IN UINTN BlockAddress
296 );
297
298 EFI_STATUS
299 NorFlashWriteSingleBlock (
300 IN UINTN DeviceBaseAddress,
301 IN EFI_LBA Lba,
302 IN UINT32 *pDataBuffer,
303 IN UINT32 BlockSizeInWords
304 );
305
306 EFI_STATUS
307 NorFlashWriteBlocks (
308 IN NOR_FLASH_INSTANCE *Instance,
309 IN EFI_LBA Lba,
310 IN UINTN BufferSizeInBytes,
311 IN VOID *Buffer
312 );
313
314 EFI_STATUS
315 NorFlashReadBlocks (
316 IN NOR_FLASH_INSTANCE *Instance,
317 IN EFI_LBA Lba,
318 IN UINTN BufferSizeInBytes,
319 OUT VOID *Buffer
320 );
321
322 EFI_STATUS
323 NorFlashReset (
324 IN NOR_FLASH_INSTANCE *Instance
325 );
326
327 #endif /* __NOR_FLASH_DXE_H__ */