2 Functions in this library instance make use of MMIO functions in IoLib to
3 access memory mapped PCI configuration space.
5 All assertions for I/O operations are handled in MMIO functions in the IoLib
8 Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>
9 This program and the accompanying materials
10 are licensed and made available under the terms and conditions of the BSD License
11 which accompanies this distribution. The full text of the license may be found at
12 http://opensource.org/licenses/bsd-license.php.
14 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
15 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
22 #include <Library/BaseLib.h>
23 #include <Library/PciExpressLib.h>
24 #include <Library/IoLib.h>
25 #include <Library/DebugLib.h>
26 #include <Library/PcdLib.h>
30 Assert the validity of a PCI address. A valid PCI address should contain 1's
31 only in the low 28 bits.
33 @param A The address to validate.
36 #define ASSERT_INVALID_PCI_ADDRESS(A) \
37 ASSERT (((A) & ~0xfffffff) == 0)
40 Registers a PCI device so PCI configuration registers may be accessed after
41 SetVirtualAddressMap().
43 Registers the PCI device specified by Address so all the PCI configuration
44 registers associated with that PCI device may be accessed after SetVirtualAddressMap()
47 If Address > 0x0FFFFFFF, then ASSERT().
49 @param Address The address that encodes the PCI Bus, Device, Function and
52 @retval RETURN_SUCCESS The PCI device was registered for runtime access.
53 @retval RETURN_UNSUPPORTED An attempt was made to call this function
54 after ExitBootServices().
55 @retval RETURN_UNSUPPORTED The resources required to access the PCI device
56 at runtime could not be mapped.
57 @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to
58 complete the registration.
63 PciExpressRegisterForRuntimeAccess (
67 ASSERT_INVALID_PCI_ADDRESS (Address
);
68 return RETURN_UNSUPPORTED
;
71 STATIC UINT64 mPciExpressBaseAddress
;
75 PciExpressLibInitialize (
79 mPciExpressBaseAddress
= PcdGet64 (PcdPciExpressBaseAddress
);
80 return RETURN_SUCCESS
;
85 Gets the base address of PCI Express.
87 @return The base address of PCI Express.
91 GetPciExpressBaseAddress (
95 return (VOID
*)(UINTN
) mPciExpressBaseAddress
;
99 Reads an 8-bit PCI configuration register.
101 Reads and returns the 8-bit PCI configuration register specified by Address.
102 This function must guarantee that all PCI read and write operations are
105 If Address > 0x0FFFFFFF, then ASSERT().
107 @param Address The address that encodes the PCI Bus, Device, Function and
110 @return The read value from the PCI configuration register.
119 ASSERT_INVALID_PCI_ADDRESS (Address
);
120 return MmioRead8 ((UINTN
) GetPciExpressBaseAddress () + Address
);
124 Writes an 8-bit PCI configuration register.
126 Writes the 8-bit PCI configuration register specified by Address with the
127 value specified by Value. Value is returned. This function must guarantee
128 that all PCI read and write operations are serialized.
130 If Address > 0x0FFFFFFF, then ASSERT().
132 @param Address The address that encodes the PCI Bus, Device, Function and
134 @param Value The value to write.
136 @return The value written to the PCI configuration register.
146 ASSERT_INVALID_PCI_ADDRESS (Address
);
147 return MmioWrite8 ((UINTN
) GetPciExpressBaseAddress () + Address
, Value
);
151 Performs a bitwise OR of an 8-bit PCI configuration register with
154 Reads the 8-bit PCI configuration register specified by Address, performs a
155 bitwise OR between the read result and the value specified by
156 OrData, and writes the result to the 8-bit PCI configuration register
157 specified by Address. The value written to the PCI configuration register is
158 returned. This function must guarantee that all PCI read and write operations
161 If Address > 0x0FFFFFFF, then ASSERT().
163 @param Address The address that encodes the PCI Bus, Device, Function and
165 @param OrData The value to OR with the PCI configuration register.
167 @return The value written back to the PCI configuration register.
177 ASSERT_INVALID_PCI_ADDRESS (Address
);
178 return MmioOr8 ((UINTN
) GetPciExpressBaseAddress () + Address
, OrData
);
182 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
185 Reads the 8-bit PCI configuration register specified by Address, performs a
186 bitwise AND between the read result and the value specified by AndData, and
187 writes the result to the 8-bit PCI configuration register specified by
188 Address. The value written to the PCI configuration register is returned.
189 This function must guarantee that all PCI read and write operations are
192 If Address > 0x0FFFFFFF, then ASSERT().
194 @param Address The address that encodes the PCI Bus, Device, Function and
196 @param AndData The value to AND with the PCI configuration register.
198 @return The value written back to the PCI configuration register.
208 ASSERT_INVALID_PCI_ADDRESS (Address
);
209 return MmioAnd8 ((UINTN
) GetPciExpressBaseAddress () + Address
, AndData
);
213 Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
214 value, followed a bitwise OR with another 8-bit value.
216 Reads the 8-bit PCI configuration register specified by Address, performs a
217 bitwise AND between the read result and the value specified by AndData,
218 performs a bitwise OR between the result of the AND operation and
219 the value specified by OrData, and writes the result to the 8-bit PCI
220 configuration register specified by Address. The value written to the PCI
221 configuration register is returned. This function must guarantee that all PCI
222 read and write operations are serialized.
224 If Address > 0x0FFFFFFF, then ASSERT().
226 @param Address The address that encodes the PCI Bus, Device, Function and
228 @param AndData The value to AND with the PCI configuration register.
229 @param OrData The value to OR with the result of the AND operation.
231 @return The value written back to the PCI configuration register.
236 PciExpressAndThenOr8 (
242 ASSERT_INVALID_PCI_ADDRESS (Address
);
243 return MmioAndThenOr8 (
244 (UINTN
) GetPciExpressBaseAddress () + Address
,
251 Reads a bit field of a PCI configuration register.
253 Reads the bit field in an 8-bit PCI configuration register. The bit field is
254 specified by the StartBit and the EndBit. The value of the bit field is
257 If Address > 0x0FFFFFFF, then ASSERT().
258 If StartBit is greater than 7, then ASSERT().
259 If EndBit is greater than 7, then ASSERT().
260 If EndBit is less than StartBit, then ASSERT().
262 @param Address The PCI configuration register to read.
263 @param StartBit The ordinal of the least significant bit in the bit field.
265 @param EndBit The ordinal of the most significant bit in the bit field.
268 @return The value of the bit field read from the PCI configuration register.
273 PciExpressBitFieldRead8 (
279 ASSERT_INVALID_PCI_ADDRESS (Address
);
280 return MmioBitFieldRead8 (
281 (UINTN
) GetPciExpressBaseAddress () + Address
,
288 Writes a bit field to a PCI configuration register.
290 Writes Value to the bit field of the PCI configuration register. The bit
291 field is specified by the StartBit and the EndBit. All other bits in the
292 destination PCI configuration register are preserved. The new value of the
293 8-bit register is returned.
295 If Address > 0x0FFFFFFF, then ASSERT().
296 If StartBit is greater than 7, then ASSERT().
297 If EndBit is greater than 7, then ASSERT().
298 If EndBit is less than StartBit, then ASSERT().
299 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
301 @param Address The PCI configuration register to write.
302 @param StartBit The ordinal of the least significant bit in the bit field.
304 @param EndBit The ordinal of the most significant bit in the bit field.
306 @param Value The new value of the bit field.
308 @return The value written back to the PCI configuration register.
313 PciExpressBitFieldWrite8 (
320 ASSERT_INVALID_PCI_ADDRESS (Address
);
321 return MmioBitFieldWrite8 (
322 (UINTN
) GetPciExpressBaseAddress () + Address
,
330 Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
331 writes the result back to the bit field in the 8-bit port.
333 Reads the 8-bit PCI configuration register specified by Address, performs a
334 bitwise OR between the read result and the value specified by
335 OrData, and writes the result to the 8-bit PCI configuration register
336 specified by Address. The value written to the PCI configuration register is
337 returned. This function must guarantee that all PCI read and write operations
338 are serialized. Extra left bits in OrData are stripped.
340 If Address > 0x0FFFFFFF, then ASSERT().
341 If StartBit is greater than 7, then ASSERT().
342 If EndBit is greater than 7, then ASSERT().
343 If EndBit is less than StartBit, then ASSERT().
344 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
346 @param Address The PCI configuration register to write.
347 @param StartBit The ordinal of the least significant bit in the bit field.
349 @param EndBit The ordinal of the most significant bit in the bit field.
351 @param OrData The value to OR with the PCI configuration register.
353 @return The value written back to the PCI configuration register.
358 PciExpressBitFieldOr8 (
365 ASSERT_INVALID_PCI_ADDRESS (Address
);
366 return MmioBitFieldOr8 (
367 (UINTN
) GetPciExpressBaseAddress () + Address
,
375 Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
376 AND, and writes the result back to the bit field in the 8-bit register.
378 Reads the 8-bit PCI configuration register specified by Address, performs a
379 bitwise AND between the read result and the value specified by AndData, and
380 writes the result to the 8-bit PCI configuration register specified by
381 Address. The value written to the PCI configuration register is returned.
382 This function must guarantee that all PCI read and write operations are
383 serialized. Extra left bits in AndData are stripped.
385 If Address > 0x0FFFFFFF, then ASSERT().
386 If StartBit is greater than 7, then ASSERT().
387 If EndBit is greater than 7, then ASSERT().
388 If EndBit is less than StartBit, then ASSERT().
389 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
391 @param Address The PCI configuration register to write.
392 @param StartBit The ordinal of the least significant bit in the bit field.
394 @param EndBit The ordinal of the most significant bit in the bit field.
396 @param AndData The value to AND with the PCI configuration register.
398 @return The value written back to the PCI configuration register.
403 PciExpressBitFieldAnd8 (
410 ASSERT_INVALID_PCI_ADDRESS (Address
);
411 return MmioBitFieldAnd8 (
412 (UINTN
) GetPciExpressBaseAddress () + Address
,
420 Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
421 bitwise OR, and writes the result back to the bit field in the
424 Reads the 8-bit PCI configuration register specified by Address, performs a
425 bitwise AND followed by a bitwise OR between the read result and
426 the value specified by AndData, and writes the result to the 8-bit PCI
427 configuration register specified by Address. The value written to the PCI
428 configuration register is returned. This function must guarantee that all PCI
429 read and write operations are serialized. Extra left bits in both AndData and
432 If Address > 0x0FFFFFFF, then ASSERT().
433 If StartBit is greater than 7, then ASSERT().
434 If EndBit is greater than 7, then ASSERT().
435 If EndBit is less than StartBit, then ASSERT().
436 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
437 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
439 @param Address The PCI configuration register to write.
440 @param StartBit The ordinal of the least significant bit in the bit field.
442 @param EndBit The ordinal of the most significant bit in the bit field.
444 @param AndData The value to AND with the PCI configuration register.
445 @param OrData The value to OR with the result of the AND operation.
447 @return The value written back to the PCI configuration register.
452 PciExpressBitFieldAndThenOr8 (
460 ASSERT_INVALID_PCI_ADDRESS (Address
);
461 return MmioBitFieldAndThenOr8 (
462 (UINTN
) GetPciExpressBaseAddress () + Address
,
471 Reads a 16-bit PCI configuration register.
473 Reads and returns the 16-bit PCI configuration register specified by Address.
474 This function must guarantee that all PCI read and write operations are
477 If Address > 0x0FFFFFFF, then ASSERT().
478 If Address is not aligned on a 16-bit boundary, then ASSERT().
480 @param Address The address that encodes the PCI Bus, Device, Function and
483 @return The read value from the PCI configuration register.
492 ASSERT_INVALID_PCI_ADDRESS (Address
);
493 return MmioRead16 ((UINTN
) GetPciExpressBaseAddress () + Address
);
497 Writes a 16-bit PCI configuration register.
499 Writes the 16-bit PCI configuration register specified by Address with the
500 value specified by Value. Value is returned. This function must guarantee
501 that all PCI read and write operations are serialized.
503 If Address > 0x0FFFFFFF, then ASSERT().
504 If Address is not aligned on a 16-bit boundary, then ASSERT().
506 @param Address The address that encodes the PCI Bus, Device, Function and
508 @param Value The value to write.
510 @return The value written to the PCI configuration register.
520 ASSERT_INVALID_PCI_ADDRESS (Address
);
521 return MmioWrite16 ((UINTN
) GetPciExpressBaseAddress () + Address
, Value
);
525 Performs a bitwise OR of a 16-bit PCI configuration register with
528 Reads the 16-bit PCI configuration register specified by Address, performs a
529 bitwise OR between the read result and the value specified by
530 OrData, and writes the result to the 16-bit PCI configuration register
531 specified by Address. The value written to the PCI configuration register is
532 returned. This function must guarantee that all PCI read and write operations
535 If Address > 0x0FFFFFFF, then ASSERT().
536 If Address is not aligned on a 16-bit boundary, then ASSERT().
538 @param Address The address that encodes the PCI Bus, Device, Function and
540 @param OrData The value to OR with the PCI configuration register.
542 @return The value written back to the PCI configuration register.
552 ASSERT_INVALID_PCI_ADDRESS (Address
);
553 return MmioOr16 ((UINTN
) GetPciExpressBaseAddress () + Address
, OrData
);
557 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
560 Reads the 16-bit PCI configuration register specified by Address, performs a
561 bitwise AND between the read result and the value specified by AndData, and
562 writes the result to the 16-bit PCI configuration register specified by
563 Address. The value written to the PCI configuration register is returned.
564 This function must guarantee that all PCI read and write operations are
567 If Address > 0x0FFFFFFF, then ASSERT().
568 If Address is not aligned on a 16-bit boundary, then ASSERT().
570 @param Address The address that encodes the PCI Bus, Device, Function and
572 @param AndData The value to AND with the PCI configuration register.
574 @return The value written back to the PCI configuration register.
584 ASSERT_INVALID_PCI_ADDRESS (Address
);
585 return MmioAnd16 ((UINTN
) GetPciExpressBaseAddress () + Address
, AndData
);
589 Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
590 value, followed a bitwise OR with another 16-bit value.
592 Reads the 16-bit PCI configuration register specified by Address, performs a
593 bitwise AND between the read result and the value specified by AndData,
594 performs a bitwise OR between the result of the AND operation and
595 the value specified by OrData, and writes the result to the 16-bit PCI
596 configuration register specified by Address. The value written to the PCI
597 configuration register is returned. This function must guarantee that all PCI
598 read and write operations are serialized.
600 If Address > 0x0FFFFFFF, then ASSERT().
601 If Address is not aligned on a 16-bit boundary, then ASSERT().
603 @param Address The address that encodes the PCI Bus, Device, Function and
605 @param AndData The value to AND with the PCI configuration register.
606 @param OrData The value to OR with the result of the AND operation.
608 @return The value written back to the PCI configuration register.
613 PciExpressAndThenOr16 (
619 ASSERT_INVALID_PCI_ADDRESS (Address
);
620 return MmioAndThenOr16 (
621 (UINTN
) GetPciExpressBaseAddress () + Address
,
628 Reads a bit field of a PCI configuration register.
630 Reads the bit field in a 16-bit PCI configuration register. The bit field is
631 specified by the StartBit and the EndBit. The value of the bit field is
634 If Address > 0x0FFFFFFF, then ASSERT().
635 If Address is not aligned on a 16-bit boundary, then ASSERT().
636 If StartBit is greater than 15, then ASSERT().
637 If EndBit is greater than 15, then ASSERT().
638 If EndBit is less than StartBit, then ASSERT().
640 @param Address The PCI configuration register to read.
641 @param StartBit The ordinal of the least significant bit in the bit field.
643 @param EndBit The ordinal of the most significant bit in the bit field.
646 @return The value of the bit field read from the PCI configuration register.
651 PciExpressBitFieldRead16 (
657 ASSERT_INVALID_PCI_ADDRESS (Address
);
658 return MmioBitFieldRead16 (
659 (UINTN
) GetPciExpressBaseAddress () + Address
,
666 Writes a bit field to a PCI configuration register.
668 Writes Value to the bit field of the PCI configuration register. The bit
669 field is specified by the StartBit and the EndBit. All other bits in the
670 destination PCI configuration register are preserved. The new value of the
671 16-bit register is returned.
673 If Address > 0x0FFFFFFF, then ASSERT().
674 If Address is not aligned on a 16-bit boundary, then ASSERT().
675 If StartBit is greater than 15, then ASSERT().
676 If EndBit is greater than 15, then ASSERT().
677 If EndBit is less than StartBit, then ASSERT().
678 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
680 @param Address The PCI configuration register to write.
681 @param StartBit The ordinal of the least significant bit in the bit field.
683 @param EndBit The ordinal of the most significant bit in the bit field.
685 @param Value The new value of the bit field.
687 @return The value written back to the PCI configuration register.
692 PciExpressBitFieldWrite16 (
699 ASSERT_INVALID_PCI_ADDRESS (Address
);
700 return MmioBitFieldWrite16 (
701 (UINTN
) GetPciExpressBaseAddress () + Address
,
709 Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
710 writes the result back to the bit field in the 16-bit port.
712 Reads the 16-bit PCI configuration register specified by Address, performs a
713 bitwise OR between the read result and the value specified by
714 OrData, and writes the result to the 16-bit PCI configuration register
715 specified by Address. The value written to the PCI configuration register is
716 returned. This function must guarantee that all PCI read and write operations
717 are serialized. Extra left bits in OrData are stripped.
719 If Address > 0x0FFFFFFF, then ASSERT().
720 If Address is not aligned on a 16-bit boundary, then ASSERT().
721 If StartBit is greater than 15, then ASSERT().
722 If EndBit is greater than 15, then ASSERT().
723 If EndBit is less than StartBit, then ASSERT().
724 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
726 @param Address The PCI configuration register to write.
727 @param StartBit The ordinal of the least significant bit in the bit field.
729 @param EndBit The ordinal of the most significant bit in the bit field.
731 @param OrData The value to OR with the PCI configuration register.
733 @return The value written back to the PCI configuration register.
738 PciExpressBitFieldOr16 (
745 ASSERT_INVALID_PCI_ADDRESS (Address
);
746 return MmioBitFieldOr16 (
747 (UINTN
) GetPciExpressBaseAddress () + Address
,
755 Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
756 AND, and writes the result back to the bit field in the 16-bit register.
758 Reads the 16-bit PCI configuration register specified by Address, performs a
759 bitwise AND between the read result and the value specified by AndData, and
760 writes the result to the 16-bit PCI configuration register specified by
761 Address. The value written to the PCI configuration register is returned.
762 This function must guarantee that all PCI read and write operations are
763 serialized. Extra left bits in AndData are stripped.
765 If Address > 0x0FFFFFFF, then ASSERT().
766 If Address is not aligned on a 16-bit boundary, then ASSERT().
767 If StartBit is greater than 15, then ASSERT().
768 If EndBit is greater than 15, then ASSERT().
769 If EndBit is less than StartBit, then ASSERT().
770 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
772 @param Address The PCI configuration register to write.
773 @param StartBit The ordinal of the least significant bit in the bit field.
775 @param EndBit The ordinal of the most significant bit in the bit field.
777 @param AndData The value to AND with the PCI configuration register.
779 @return The value written back to the PCI configuration register.
784 PciExpressBitFieldAnd16 (
791 ASSERT_INVALID_PCI_ADDRESS (Address
);
792 return MmioBitFieldAnd16 (
793 (UINTN
) GetPciExpressBaseAddress () + Address
,
801 Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
802 bitwise OR, and writes the result back to the bit field in the
805 Reads the 16-bit PCI configuration register specified by Address, performs a
806 bitwise AND followed by a bitwise OR between the read result and
807 the value specified by AndData, and writes the result to the 16-bit PCI
808 configuration register specified by Address. The value written to the PCI
809 configuration register is returned. This function must guarantee that all PCI
810 read and write operations are serialized. Extra left bits in both AndData and
813 If Address > 0x0FFFFFFF, then ASSERT().
814 If Address is not aligned on a 16-bit boundary, then ASSERT().
815 If StartBit is greater than 15, then ASSERT().
816 If EndBit is greater than 15, then ASSERT().
817 If EndBit is less than StartBit, then ASSERT().
818 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
819 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
821 @param Address The PCI configuration register to write.
822 @param StartBit The ordinal of the least significant bit in the bit field.
824 @param EndBit The ordinal of the most significant bit in the bit field.
826 @param AndData The value to AND with the PCI configuration register.
827 @param OrData The value to OR with the result of the AND operation.
829 @return The value written back to the PCI configuration register.
834 PciExpressBitFieldAndThenOr16 (
842 ASSERT_INVALID_PCI_ADDRESS (Address
);
843 return MmioBitFieldAndThenOr16 (
844 (UINTN
) GetPciExpressBaseAddress () + Address
,
853 Reads a 32-bit PCI configuration register.
855 Reads and returns the 32-bit PCI configuration register specified by Address.
856 This function must guarantee that all PCI read and write operations are
859 If Address > 0x0FFFFFFF, then ASSERT().
860 If Address is not aligned on a 32-bit boundary, then ASSERT().
862 @param Address The address that encodes the PCI Bus, Device, Function and
865 @return The read value from the PCI configuration register.
874 ASSERT_INVALID_PCI_ADDRESS (Address
);
875 return MmioRead32 ((UINTN
) GetPciExpressBaseAddress () + Address
);
879 Writes a 32-bit PCI configuration register.
881 Writes the 32-bit PCI configuration register specified by Address with the
882 value specified by Value. Value is returned. This function must guarantee
883 that all PCI read and write operations are serialized.
885 If Address > 0x0FFFFFFF, then ASSERT().
886 If Address is not aligned on a 32-bit boundary, then ASSERT().
888 @param Address The address that encodes the PCI Bus, Device, Function and
890 @param Value The value to write.
892 @return The value written to the PCI configuration register.
902 ASSERT_INVALID_PCI_ADDRESS (Address
);
903 return MmioWrite32 ((UINTN
) GetPciExpressBaseAddress () + Address
, Value
);
907 Performs a bitwise OR of a 32-bit PCI configuration register with
910 Reads the 32-bit PCI configuration register specified by Address, performs a
911 bitwise OR between the read result and the value specified by
912 OrData, and writes the result to the 32-bit PCI configuration register
913 specified by Address. The value written to the PCI configuration register is
914 returned. This function must guarantee that all PCI read and write operations
917 If Address > 0x0FFFFFFF, then ASSERT().
918 If Address is not aligned on a 32-bit boundary, then ASSERT().
920 @param Address The address that encodes the PCI Bus, Device, Function and
922 @param OrData The value to OR with the PCI configuration register.
924 @return The value written back to the PCI configuration register.
934 ASSERT_INVALID_PCI_ADDRESS (Address
);
935 return MmioOr32 ((UINTN
) GetPciExpressBaseAddress () + Address
, OrData
);
939 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
942 Reads the 32-bit PCI configuration register specified by Address, performs a
943 bitwise AND between the read result and the value specified by AndData, and
944 writes the result to the 32-bit PCI configuration register specified by
945 Address. The value written to the PCI configuration register is returned.
946 This function must guarantee that all PCI read and write operations are
949 If Address > 0x0FFFFFFF, then ASSERT().
950 If Address is not aligned on a 32-bit boundary, then ASSERT().
952 @param Address The address that encodes the PCI Bus, Device, Function and
954 @param AndData The value to AND with the PCI configuration register.
956 @return The value written back to the PCI configuration register.
966 ASSERT_INVALID_PCI_ADDRESS (Address
);
967 return MmioAnd32 ((UINTN
) GetPciExpressBaseAddress () + Address
, AndData
);
971 Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
972 value, followed a bitwise OR with another 32-bit value.
974 Reads the 32-bit PCI configuration register specified by Address, performs a
975 bitwise AND between the read result and the value specified by AndData,
976 performs a bitwise OR between the result of the AND operation and
977 the value specified by OrData, and writes the result to the 32-bit PCI
978 configuration register specified by Address. The value written to the PCI
979 configuration register is returned. This function must guarantee that all PCI
980 read and write operations are serialized.
982 If Address > 0x0FFFFFFF, then ASSERT().
983 If Address is not aligned on a 32-bit boundary, then ASSERT().
985 @param Address The address that encodes the PCI Bus, Device, Function and
987 @param AndData The value to AND with the PCI configuration register.
988 @param OrData The value to OR with the result of the AND operation.
990 @return The value written back to the PCI configuration register.
995 PciExpressAndThenOr32 (
1001 ASSERT_INVALID_PCI_ADDRESS (Address
);
1002 return MmioAndThenOr32 (
1003 (UINTN
) GetPciExpressBaseAddress () + Address
,
1010 Reads a bit field of a PCI configuration register.
1012 Reads the bit field in a 32-bit PCI configuration register. The bit field is
1013 specified by the StartBit and the EndBit. The value of the bit field is
1016 If Address > 0x0FFFFFFF, then ASSERT().
1017 If Address is not aligned on a 32-bit boundary, then ASSERT().
1018 If StartBit is greater than 31, then ASSERT().
1019 If EndBit is greater than 31, then ASSERT().
1020 If EndBit is less than StartBit, then ASSERT().
1022 @param Address The PCI configuration register to read.
1023 @param StartBit The ordinal of the least significant bit in the bit field.
1025 @param EndBit The ordinal of the most significant bit in the bit field.
1028 @return The value of the bit field read from the PCI configuration register.
1033 PciExpressBitFieldRead32 (
1039 ASSERT_INVALID_PCI_ADDRESS (Address
);
1040 return MmioBitFieldRead32 (
1041 (UINTN
) GetPciExpressBaseAddress () + Address
,
1048 Writes a bit field to a PCI configuration register.
1050 Writes Value to the bit field of the PCI configuration register. The bit
1051 field is specified by the StartBit and the EndBit. All other bits in the
1052 destination PCI configuration register are preserved. The new value of the
1053 32-bit register is returned.
1055 If Address > 0x0FFFFFFF, then ASSERT().
1056 If Address is not aligned on a 32-bit boundary, then ASSERT().
1057 If StartBit is greater than 31, then ASSERT().
1058 If EndBit is greater than 31, then ASSERT().
1059 If EndBit is less than StartBit, then ASSERT().
1060 If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1062 @param Address The PCI configuration register to write.
1063 @param StartBit The ordinal of the least significant bit in the bit field.
1065 @param EndBit The ordinal of the most significant bit in the bit field.
1067 @param Value The new value of the bit field.
1069 @return The value written back to the PCI configuration register.
1074 PciExpressBitFieldWrite32 (
1081 ASSERT_INVALID_PCI_ADDRESS (Address
);
1082 return MmioBitFieldWrite32 (
1083 (UINTN
) GetPciExpressBaseAddress () + Address
,
1091 Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
1092 writes the result back to the bit field in the 32-bit port.
1094 Reads the 32-bit PCI configuration register specified by Address, performs a
1095 bitwise OR between the read result and the value specified by
1096 OrData, and writes the result to the 32-bit PCI configuration register
1097 specified by Address. The value written to the PCI configuration register is
1098 returned. This function must guarantee that all PCI read and write operations
1099 are serialized. Extra left bits in OrData are stripped.
1101 If Address > 0x0FFFFFFF, then ASSERT().
1102 If Address is not aligned on a 32-bit boundary, then ASSERT().
1103 If StartBit is greater than 31, then ASSERT().
1104 If EndBit is greater than 31, then ASSERT().
1105 If EndBit is less than StartBit, then ASSERT().
1106 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1108 @param Address The PCI configuration register to write.
1109 @param StartBit The ordinal of the least significant bit in the bit field.
1111 @param EndBit The ordinal of the most significant bit in the bit field.
1113 @param OrData The value to OR with the PCI configuration register.
1115 @return The value written back to the PCI configuration register.
1120 PciExpressBitFieldOr32 (
1127 ASSERT_INVALID_PCI_ADDRESS (Address
);
1128 return MmioBitFieldOr32 (
1129 (UINTN
) GetPciExpressBaseAddress () + Address
,
1137 Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
1138 AND, and writes the result back to the bit field in the 32-bit register.
1140 Reads the 32-bit PCI configuration register specified by Address, performs a
1141 bitwise AND between the read result and the value specified by AndData, and
1142 writes the result to the 32-bit PCI configuration register specified by
1143 Address. The value written to the PCI configuration register is returned.
1144 This function must guarantee that all PCI read and write operations are
1145 serialized. Extra left bits in AndData are stripped.
1147 If Address > 0x0FFFFFFF, then ASSERT().
1148 If Address is not aligned on a 32-bit boundary, then ASSERT().
1149 If StartBit is greater than 31, then ASSERT().
1150 If EndBit is greater than 31, then ASSERT().
1151 If EndBit is less than StartBit, then ASSERT().
1152 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1154 @param Address The PCI configuration register to write.
1155 @param StartBit The ordinal of the least significant bit in the bit field.
1157 @param EndBit The ordinal of the most significant bit in the bit field.
1159 @param AndData The value to AND with the PCI configuration register.
1161 @return The value written back to the PCI configuration register.
1166 PciExpressBitFieldAnd32 (
1173 ASSERT_INVALID_PCI_ADDRESS (Address
);
1174 return MmioBitFieldAnd32 (
1175 (UINTN
) GetPciExpressBaseAddress () + Address
,
1183 Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
1184 bitwise OR, and writes the result back to the bit field in the
1187 Reads the 32-bit PCI configuration register specified by Address, performs a
1188 bitwise AND followed by a bitwise OR between the read result and
1189 the value specified by AndData, and writes the result to the 32-bit PCI
1190 configuration register specified by Address. The value written to the PCI
1191 configuration register is returned. This function must guarantee that all PCI
1192 read and write operations are serialized. Extra left bits in both AndData and
1193 OrData are stripped.
1195 If Address > 0x0FFFFFFF, then ASSERT().
1196 If Address is not aligned on a 32-bit boundary, then ASSERT().
1197 If StartBit is greater than 31, then ASSERT().
1198 If EndBit is greater than 31, then ASSERT().
1199 If EndBit is less than StartBit, then ASSERT().
1200 If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1201 If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().
1203 @param Address The PCI configuration register to write.
1204 @param StartBit The ordinal of the least significant bit in the bit field.
1206 @param EndBit The ordinal of the most significant bit in the bit field.
1208 @param AndData The value to AND with the PCI configuration register.
1209 @param OrData The value to OR with the result of the AND operation.
1211 @return The value written back to the PCI configuration register.
1216 PciExpressBitFieldAndThenOr32 (
1224 ASSERT_INVALID_PCI_ADDRESS (Address
);
1225 return MmioBitFieldAndThenOr32 (
1226 (UINTN
) GetPciExpressBaseAddress () + Address
,
1235 Reads a range of PCI configuration registers into a caller supplied buffer.
1237 Reads the range of PCI configuration registers specified by StartAddress and
1238 Size into the buffer specified by Buffer. This function only allows the PCI
1239 configuration registers from a single PCI function to be read. Size is
1240 returned. When possible 32-bit PCI configuration read cycles are used to read
1241 from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
1242 and 16-bit PCI configuration read cycles may be used at the beginning and the
1245 If StartAddress > 0x0FFFFFFF, then ASSERT().
1246 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1247 If Size > 0 and Buffer is NULL, then ASSERT().
1249 @param StartAddress The starting address that encodes the PCI Bus, Device,
1250 Function and Register.
1251 @param Size The size in bytes of the transfer.
1252 @param Buffer The pointer to a buffer receiving the data read.
1254 @return Size read data from StartAddress.
1259 PciExpressReadBuffer (
1260 IN UINTN StartAddress
,
1267 ASSERT_INVALID_PCI_ADDRESS (StartAddress
);
1268 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1274 ASSERT (Buffer
!= NULL
);
1277 // Save Size for return
1281 if ((StartAddress
& 1) != 0) {
1283 // Read a byte if StartAddress is byte aligned
1285 *(volatile UINT8
*)Buffer
= PciExpressRead8 (StartAddress
);
1286 StartAddress
+= sizeof (UINT8
);
1287 Size
-= sizeof (UINT8
);
1288 Buffer
= (UINT8
*)Buffer
+ 1;
1291 if (Size
>= sizeof (UINT16
) && (StartAddress
& 2) != 0) {
1293 // Read a word if StartAddress is word aligned
1295 WriteUnaligned16 ((UINT16
*) Buffer
, (UINT16
) PciExpressRead16 (StartAddress
));
1297 StartAddress
+= sizeof (UINT16
);
1298 Size
-= sizeof (UINT16
);
1299 Buffer
= (UINT16
*)Buffer
+ 1;
1302 while (Size
>= sizeof (UINT32
)) {
1304 // Read as many double words as possible
1306 WriteUnaligned32 ((UINT32
*) Buffer
, (UINT32
) PciExpressRead32 (StartAddress
));
1308 StartAddress
+= sizeof (UINT32
);
1309 Size
-= sizeof (UINT32
);
1310 Buffer
= (UINT32
*)Buffer
+ 1;
1313 if (Size
>= sizeof (UINT16
)) {
1315 // Read the last remaining word if exist
1317 WriteUnaligned16 ((UINT16
*) Buffer
, (UINT16
) PciExpressRead16 (StartAddress
));
1318 StartAddress
+= sizeof (UINT16
);
1319 Size
-= sizeof (UINT16
);
1320 Buffer
= (UINT16
*)Buffer
+ 1;
1323 if (Size
>= sizeof (UINT8
)) {
1325 // Read the last remaining byte if exist
1327 *(volatile UINT8
*)Buffer
= PciExpressRead8 (StartAddress
);
1334 Copies the data in a caller supplied buffer to a specified range of PCI
1335 configuration space.
1337 Writes the range of PCI configuration registers specified by StartAddress and
1338 Size from the buffer specified by Buffer. This function only allows the PCI
1339 configuration registers from a single PCI function to be written. Size is
1340 returned. When possible 32-bit PCI configuration write cycles are used to
1341 write from StartAdress to StartAddress + Size. Due to alignment restrictions,
1342 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
1343 and the end of the range.
1345 If StartAddress > 0x0FFFFFFF, then ASSERT().
1346 If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
1347 If Size > 0 and Buffer is NULL, then ASSERT().
1349 @param StartAddress The starting address that encodes the PCI Bus, Device,
1350 Function and Register.
1351 @param Size The size in bytes of the transfer.
1352 @param Buffer The pointer to a buffer containing the data to write.
1354 @return Size written to StartAddress.
1359 PciExpressWriteBuffer (
1360 IN UINTN StartAddress
,
1367 ASSERT_INVALID_PCI_ADDRESS (StartAddress
);
1368 ASSERT (((StartAddress
& 0xFFF) + Size
) <= 0x1000);
1374 ASSERT (Buffer
!= NULL
);
1377 // Save Size for return
1381 if ((StartAddress
& 1) != 0) {
1383 // Write a byte if StartAddress is byte aligned
1385 PciExpressWrite8 (StartAddress
, *(UINT8
*)Buffer
);
1386 StartAddress
+= sizeof (UINT8
);
1387 Size
-= sizeof (UINT8
);
1388 Buffer
= (UINT8
*)Buffer
+ 1;
1391 if (Size
>= sizeof (UINT16
) && (StartAddress
& 2) != 0) {
1393 // Write a word if StartAddress is word aligned
1395 PciExpressWrite16 (StartAddress
, ReadUnaligned16 ((UINT16
*)Buffer
));
1396 StartAddress
+= sizeof (UINT16
);
1397 Size
-= sizeof (UINT16
);
1398 Buffer
= (UINT16
*)Buffer
+ 1;
1401 while (Size
>= sizeof (UINT32
)) {
1403 // Write as many double words as possible
1405 PciExpressWrite32 (StartAddress
, ReadUnaligned32 ((UINT32
*)Buffer
));
1406 StartAddress
+= sizeof (UINT32
);
1407 Size
-= sizeof (UINT32
);
1408 Buffer
= (UINT32
*)Buffer
+ 1;
1411 if (Size
>= sizeof (UINT16
)) {
1413 // Write the last remaining word if exist
1415 PciExpressWrite16 (StartAddress
, ReadUnaligned16 ((UINT16
*)Buffer
));
1416 StartAddress
+= sizeof (UINT16
);
1417 Size
-= sizeof (UINT16
);
1418 Buffer
= (UINT16
*)Buffer
+ 1;
1421 if (Size
>= sizeof (UINT8
)) {
1423 // Write the last remaining byte if exist
1425 PciExpressWrite8 (StartAddress
, *(UINT8
*)Buffer
);