2 * Device tree enumeration DXE driver for ARM Virtual Machines
4 * Copyright (c) 2014, Linaro Ltd. All rights reserved.<BR>
6 * This program and the accompanying materials are
7 * licensed and made available under the terms and conditions of the BSD License
8 * which accompanies this distribution. The full text of the license may be found at
9 * http://opensource.org/licenses/bsd-license.php
11 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
16 #include <Library/BaseLib.h>
17 #include <Library/DebugLib.h>
18 #include <Library/UefiLib.h>
19 #include <Library/BaseMemoryLib.h>
20 #include <Library/UefiDriverEntryPoint.h>
21 #include <Library/MemoryAllocationLib.h>
22 #include <Library/UefiBootServicesTableLib.h>
23 #include <Library/VirtioMmioDeviceLib.h>
24 #include <Library/DevicePathLib.h>
25 #include <Library/PcdLib.h>
26 #include <Library/DxeServicesLib.h>
30 #include <Guid/VirtioMmioTransport.h>
34 VENDOR_DEVICE_PATH Vendor
;
36 EFI_DEVICE_PATH_PROTOCOL End
;
37 } VIRTIO_TRANSPORT_DEVICE_PATH
;
58 STATIC CONST PROPERTY CompatibleProperties
[] = {
59 { PropertyTypeGic
, "arm,cortex-a15-gic" },
60 { PropertyTypeRtc
, "arm,pl031" },
61 { PropertyTypeVirtio
, "virtio,mmio" },
62 { PropertyTypeUart
, "arm,pl011" },
63 { PropertyTypeTimer
, "arm,armv7-timer" },
64 { PropertyTypeTimer
, "arm,armv8-timer" },
65 { PropertyTypePsci
, "arm,psci-0.2" },
66 { PropertyTypeFwCfg
, "qemu,fw-cfg-mmio" },
67 { PropertyTypePciHost
, "pci-host-ecam-generic" },
68 { PropertyTypeGicV3
, "arm,gic-v3" },
69 { PropertyTypeUnknown
, "" }
81 IN CONST CHAR8
*NodeType
,
85 CONST CHAR8
*Compatible
;
86 CONST PROPERTY
*CompatibleProperty
;
89 // A 'compatible' node may contain a sequence of NULL terminated
90 // compatible strings so check each one
92 for (Compatible
= NodeType
; Compatible
< NodeType
+ Size
&& *Compatible
;
93 Compatible
+= 1 + AsciiStrLen (Compatible
)) {
94 for (CompatibleProperty
= CompatibleProperties
; CompatibleProperty
->Compatible
[0]; CompatibleProperty
++) {
95 if (AsciiStrCmp (CompatibleProperty
->Compatible
, Compatible
) == 0) {
96 return CompatibleProperty
->Type
;
100 return PropertyTypeUnknown
;
104 // We expect the "ranges" property of "pci-host-ecam-generic" to consist of
105 // records like this.
113 } DTB_PCI_HOST_RANGE_RECORD
;
116 #define DTB_PCI_HOST_RANGE_RELOCATABLE BIT31
117 #define DTB_PCI_HOST_RANGE_PREFETCHABLE BIT30
118 #define DTB_PCI_HOST_RANGE_ALIASED BIT29
119 #define DTB_PCI_HOST_RANGE_MMIO32 BIT25
120 #define DTB_PCI_HOST_RANGE_MMIO64 (BIT25 | BIT24)
121 #define DTB_PCI_HOST_RANGE_IO BIT24
122 #define DTB_PCI_HOST_RANGE_TYPEMASK (BIT31 | BIT30 | BIT29 | BIT25 | BIT24)
125 Process the device tree node describing the generic PCI host controller.
127 param[in] DeviceTreeBase Pointer to the device tree.
129 param[in] Node Offset of the device tree node whose "compatible"
130 property is "pci-host-ecam-generic".
132 param[in] RegProp Pointer to the "reg" property of Node. The caller
133 is responsible for ensuring that the size of the
134 property is 4 UINT32 cells.
136 @retval EFI_SUCCESS Parsing successful, properties parsed from Node
137 have been stored in dynamic PCDs.
139 @retval EFI_PROTOCOL_ERROR Parsing failed. PCDs are left unchanged.
145 IN CONST VOID
*DeviceTreeBase
,
147 IN CONST VOID
*RegProp
150 UINT64 ConfigBase
, ConfigSize
;
153 UINT32 BusMin
, BusMax
;
155 UINT64 IoBase
, IoSize
, IoTranslation
;
156 UINT64 MmioBase
, MmioSize
, MmioTranslation
;
159 // Fetch the ECAM window.
161 ConfigBase
= fdt64_to_cpu (((CONST UINT64
*)RegProp
)[0]);
162 ConfigSize
= fdt64_to_cpu (((CONST UINT64
*)RegProp
)[1]);
165 // Fetch the bus range (note: inclusive).
167 Prop
= fdt_getprop (DeviceTreeBase
, Node
, "bus-range", &Len
);
168 if (Prop
== NULL
|| Len
!= 2 * sizeof(UINT32
)) {
169 DEBUG ((EFI_D_ERROR
, "%a: 'bus-range' not found or invalid\n",
171 return EFI_PROTOCOL_ERROR
;
173 BusMin
= fdt32_to_cpu (((CONST UINT32
*)Prop
)[0]);
174 BusMax
= fdt32_to_cpu (((CONST UINT32
*)Prop
)[1]);
177 // Sanity check: the config space must accommodate all 4K register bytes of
178 // all 8 functions of all 32 devices of all buses.
180 if (BusMax
< BusMin
|| BusMax
- BusMin
== MAX_UINT32
||
181 DivU64x32 (ConfigSize
, SIZE_4KB
* 8 * 32) < BusMax
- BusMin
+ 1) {
182 DEBUG ((EFI_D_ERROR
, "%a: invalid 'bus-range' and/or 'reg'\n",
184 return EFI_PROTOCOL_ERROR
;
188 // Iterate over "ranges".
190 Prop
= fdt_getprop (DeviceTreeBase
, Node
, "ranges", &Len
);
191 if (Prop
== NULL
|| Len
== 0 ||
192 Len
% sizeof (DTB_PCI_HOST_RANGE_RECORD
) != 0) {
193 DEBUG ((EFI_D_ERROR
, "%a: 'ranges' not found or invalid\n", __FUNCTION__
));
194 return EFI_PROTOCOL_ERROR
;
198 // IoBase, IoTranslation, MmioBase and MmioTranslation are initialized only
199 // in order to suppress '-Werror=maybe-uninitialized' warnings *incorrectly*
200 // emitted by some gcc versions.
208 // IoSize and MmioSize are initialized to zero because the logic below
213 for (RecordIdx
= 0; RecordIdx
< Len
/ sizeof (DTB_PCI_HOST_RANGE_RECORD
);
215 CONST DTB_PCI_HOST_RANGE_RECORD
*Record
;
217 Record
= (CONST DTB_PCI_HOST_RANGE_RECORD
*)Prop
+ RecordIdx
;
218 switch (fdt32_to_cpu (Record
->Type
) & DTB_PCI_HOST_RANGE_TYPEMASK
) {
219 case DTB_PCI_HOST_RANGE_IO
:
220 IoBase
= fdt64_to_cpu (Record
->ChildBase
);
221 IoSize
= fdt64_to_cpu (Record
->Size
);
222 IoTranslation
= fdt64_to_cpu (Record
->CpuBase
) - IoBase
;
225 case DTB_PCI_HOST_RANGE_MMIO32
:
226 MmioBase
= fdt64_to_cpu (Record
->ChildBase
);
227 MmioSize
= fdt64_to_cpu (Record
->Size
);
228 MmioTranslation
= fdt64_to_cpu (Record
->CpuBase
) - MmioBase
;
230 if (MmioBase
> MAX_UINT32
|| MmioSize
> MAX_UINT32
||
231 MmioBase
+ MmioSize
> SIZE_4GB
) {
232 DEBUG ((EFI_D_ERROR
, "%a: MMIO32 space invalid\n", __FUNCTION__
));
233 return EFI_PROTOCOL_ERROR
;
236 if (MmioTranslation
!= 0) {
237 DEBUG ((EFI_D_ERROR
, "%a: unsupported nonzero MMIO32 translation "
238 "0x%Lx\n", __FUNCTION__
, MmioTranslation
));
239 return EFI_UNSUPPORTED
;
245 if (IoSize
== 0 || MmioSize
== 0) {
246 DEBUG ((EFI_D_ERROR
, "%a: %a space empty\n", __FUNCTION__
,
247 (IoSize
== 0) ? "IO" : "MMIO32"));
248 return EFI_PROTOCOL_ERROR
;
251 PcdSet64 (PcdPciExpressBaseAddress
, ConfigBase
);
253 PcdSet32 (PcdPciBusMin
, BusMin
);
254 PcdSet32 (PcdPciBusMax
, BusMax
);
256 PcdSet64 (PcdPciIoBase
, IoBase
);
257 PcdSet64 (PcdPciIoSize
, IoSize
);
258 PcdSet64 (PcdPciIoTranslation
, IoTranslation
);
260 PcdSet32 (PcdPciMmio32Base
, (UINT32
)MmioBase
);
261 PcdSet32 (PcdPciMmio32Size
, (UINT32
)MmioSize
);
263 PcdSetBool (PcdPciDisableBusEnumeration
, FALSE
);
265 DEBUG ((EFI_D_INFO
, "%a: Config[0x%Lx+0x%Lx) Bus[0x%x..0x%x] "
266 "Io[0x%Lx+0x%Lx)@0x%Lx Mem[0x%Lx+0x%Lx)@0x%Lx\n", __FUNCTION__
, ConfigBase
,
267 ConfigSize
, BusMin
, BusMax
, IoBase
, IoSize
, IoTranslation
, MmioBase
,
268 MmioSize
, MmioTranslation
));
275 InitializeVirtFdtDxe (
276 IN EFI_HANDLE ImageHandle
,
277 IN EFI_SYSTEM_TABLE
*SystemTable
280 VOID
*DeviceTreeBase
;
286 PROPERTY_TYPE PropType
;
288 VIRTIO_TRANSPORT_DEVICE_PATH
*DevicePath
;
291 UINT64 DistBase
, CpuBase
, RedistBase
;
292 CONST INTERRUPT_PROPERTY
*InterruptProp
;
293 INT32 SecIntrNum
, IntrNum
, VirtIntrNum
, HypIntrNum
;
294 CONST CHAR8
*PsciMethod
;
295 UINT64 FwCfgSelectorAddress
;
296 UINT64 FwCfgSelectorSize
;
297 UINT64 FwCfgDataAddress
;
298 UINT64 FwCfgDataSize
;
300 DeviceTreeBase
= (VOID
*)(UINTN
)PcdGet64 (PcdDeviceTreeBaseAddress
);
301 ASSERT (DeviceTreeBase
!= NULL
);
303 if (fdt_check_header (DeviceTreeBase
) != 0) {
304 DEBUG ((EFI_D_ERROR
, "%a: No DTB found @ 0x%p\n", __FUNCTION__
, DeviceTreeBase
));
305 return EFI_NOT_FOUND
;
308 Status
= gBS
->InstallConfigurationTable (&gFdtTableGuid
, DeviceTreeBase
);
309 ASSERT_EFI_ERROR (Status
);
311 DEBUG ((EFI_D_INFO
, "%a: DTB @ 0x%p\n", __FUNCTION__
, DeviceTreeBase
));
315 // Now enumerate the nodes and install peripherals that we are interested in,
316 // i.e., GIC, RTC and virtio MMIO nodes
318 for (Prev
= 0;; Prev
= Node
) {
319 Node
= fdt_next_node (DeviceTreeBase
, Prev
, NULL
);
324 Type
= fdt_getprop (DeviceTreeBase
, Node
, "compatible", &Len
);
329 PropType
= GetTypeFromNode (Type
, Len
);
330 if (PropType
== PropertyTypeUnknown
) {
335 // Get the 'reg' property of this node. For now, we will assume
336 // 8 byte quantities for base and size, respectively.
337 // TODO use #cells root properties instead
339 RegProp
= fdt_getprop (DeviceTreeBase
, Node
, "reg", &Len
);
340 ASSERT ((RegProp
!= NULL
) || (PropType
== PropertyTypeTimer
) ||
341 (PropType
== PropertyTypePsci
));
344 case PropertyTypePciHost
:
345 ASSERT (Len
== 2 * sizeof (UINT64
));
346 Status
= ProcessPciHost (DeviceTreeBase
, Node
, RegProp
);
347 ASSERT_EFI_ERROR (Status
);
350 case PropertyTypeFwCfg
:
351 ASSERT (Len
== 2 * sizeof (UINT64
));
353 FwCfgDataAddress
= fdt64_to_cpu (((UINT64
*)RegProp
)[0]);
355 FwCfgSelectorAddress
= FwCfgDataAddress
+ FwCfgDataSize
;
356 FwCfgSelectorSize
= 2;
359 // The following ASSERT()s express
361 // Address + Size - 1 <= MAX_UINTN
363 // for both registers, that is, that the last byte in each MMIO range is
364 // expressible as a MAX_UINTN. The form below is mathematically
365 // equivalent, and it also prevents any unsigned overflow before the
368 ASSERT (FwCfgSelectorAddress
<= MAX_UINTN
- FwCfgSelectorSize
+ 1);
369 ASSERT (FwCfgDataAddress
<= MAX_UINTN
- FwCfgDataSize
+ 1);
371 PcdSet64 (PcdFwCfgSelectorAddress
, FwCfgSelectorAddress
);
372 PcdSet64 (PcdFwCfgDataAddress
, FwCfgDataAddress
);
374 DEBUG ((EFI_D_INFO
, "Found FwCfg @ 0x%Lx/0x%Lx\n", FwCfgSelectorAddress
,
378 case PropertyTypeVirtio
:
381 // Create a unique device path for this transport on the fly
383 RegBase
= fdt64_to_cpu (((UINT64
*)RegProp
)[0]);
384 DevicePath
= (VIRTIO_TRANSPORT_DEVICE_PATH
*)CreateDeviceNode (
385 HARDWARE_DEVICE_PATH
,
387 sizeof (VIRTIO_TRANSPORT_DEVICE_PATH
));
388 if (DevicePath
== NULL
) {
389 DEBUG ((EFI_D_ERROR
, "%a: Out of memory\n", __FUNCTION__
));
393 CopyMem (&DevicePath
->Vendor
.Guid
, &gVirtioMmioTransportGuid
,
395 DevicePath
->PhysBase
= RegBase
;
396 SetDevicePathNodeLength (&DevicePath
->Vendor
,
397 sizeof (*DevicePath
) - sizeof (DevicePath
->End
));
398 SetDevicePathEndNode (&DevicePath
->End
);
401 Status
= gBS
->InstallProtocolInterface (&Handle
,
402 &gEfiDevicePathProtocolGuid
, EFI_NATIVE_INTERFACE
,
404 if (EFI_ERROR (Status
)) {
405 DEBUG ((EFI_D_ERROR
, "%a: Failed to install the EFI_DEVICE_PATH "
406 "protocol on a new handle (Status == %r)\n",
407 __FUNCTION__
, Status
));
408 FreePool (DevicePath
);
412 Status
= VirtioMmioInstallDevice (RegBase
, Handle
);
413 if (EFI_ERROR (Status
)) {
414 DEBUG ((EFI_D_ERROR
, "%a: Failed to install VirtIO transport @ 0x%Lx "
415 "on handle %p (Status == %r)\n", __FUNCTION__
, RegBase
,
418 Status
= gBS
->UninstallProtocolInterface (Handle
,
419 &gEfiDevicePathProtocolGuid
, DevicePath
);
420 ASSERT_EFI_ERROR (Status
);
421 FreePool (DevicePath
);
425 case PropertyTypeGic
:
428 DistBase
= fdt64_to_cpu (((UINT64
*)RegProp
)[0]);
429 CpuBase
= fdt64_to_cpu (((UINT64
*)RegProp
)[2]);
430 ASSERT (DistBase
< MAX_UINT32
);
431 ASSERT (CpuBase
< MAX_UINT32
);
433 PcdSet32 (PcdGicDistributorBase
, (UINT32
)DistBase
);
434 PcdSet32 (PcdGicInterruptInterfaceBase
, (UINT32
)CpuBase
);
436 DEBUG ((EFI_D_INFO
, "Found GIC @ 0x%Lx/0x%Lx\n", DistBase
, CpuBase
));
439 case PropertyTypeGicV3
:
441 // The GIC v3 DT binding describes a series of at least 3 physical (base
442 // addresses, size) pairs: the distributor interface (GICD), at least one
443 // redistributor region (GICR) containing dedicated redistributor
444 // interfaces for all individual CPUs, and the CPU interface (GICC).
445 // Under virtualization, we assume that the first redistributor region
446 // listed covers the boot CPU. Also, our GICv3 driver only supports the
447 // system register CPU interface, so we can safely ignore the MMIO version
448 // which is listed after the sequence of redistributor interfaces.
449 // This means we are only interested in the first two memory regions
450 // supplied, and ignore everything else.
454 // RegProp[0..1] == { GICD base, GICD size }
455 DistBase
= fdt64_to_cpu (((UINT64
*)RegProp
)[0]);
456 ASSERT (DistBase
< MAX_UINT32
);
458 // RegProp[2..3] == { GICR base, GICR size }
459 RedistBase
= fdt64_to_cpu (((UINT64
*)RegProp
)[2]);
460 ASSERT (RedistBase
< MAX_UINT32
);
462 PcdSet32 (PcdGicDistributorBase
, (UINT32
)DistBase
);
463 PcdSet32 (PcdGicRedistributorsBase
, (UINT32
)RedistBase
);
465 DEBUG ((EFI_D_INFO
, "Found GIC v3 (re)distributor @ 0x%Lx (0x%Lx)\n",
466 DistBase
, RedistBase
));
469 case PropertyTypeRtc
:
472 RegBase
= fdt64_to_cpu (((UINT64
*)RegProp
)[0]);
473 ASSERT (RegBase
< MAX_UINT32
);
475 PcdSet32 (PcdPL031RtcBase
, (UINT32
)RegBase
);
477 DEBUG ((EFI_D_INFO
, "Found PL031 RTC @ 0x%Lx\n", RegBase
));
481 case PropertyTypeTimer
:
483 // - interrupts : Interrupt list for secure, non-secure, virtual and
484 // hypervisor timers, in that order.
486 InterruptProp
= fdt_getprop (DeviceTreeBase
, Node
, "interrupts", &Len
);
487 ASSERT (Len
== 36 || Len
== 48);
489 SecIntrNum
= fdt32_to_cpu (InterruptProp
[0].Number
)
490 + (InterruptProp
[0].Type
? 16 : 0);
491 IntrNum
= fdt32_to_cpu (InterruptProp
[1].Number
)
492 + (InterruptProp
[1].Type
? 16 : 0);
493 VirtIntrNum
= fdt32_to_cpu (InterruptProp
[2].Number
)
494 + (InterruptProp
[2].Type
? 16 : 0);
495 HypIntrNum
= Len
< 48 ? 0 : fdt32_to_cpu (InterruptProp
[3].Number
)
496 + (InterruptProp
[3].Type
? 16 : 0);
498 DEBUG ((EFI_D_INFO
, "Found Timer interrupts %d, %d, %d, %d\n",
499 SecIntrNum
, IntrNum
, VirtIntrNum
, HypIntrNum
));
501 PcdSet32 (PcdArmArchTimerSecIntrNum
, SecIntrNum
);
502 PcdSet32 (PcdArmArchTimerIntrNum
, IntrNum
);
503 PcdSet32 (PcdArmArchTimerVirtIntrNum
, VirtIntrNum
);
504 PcdSet32 (PcdArmArchTimerHypIntrNum
, HypIntrNum
);
507 case PropertyTypePsci
:
508 PsciMethod
= fdt_getprop (DeviceTreeBase
, Node
, "method", &Len
);
510 if (PsciMethod
&& AsciiStrnCmp (PsciMethod
, "hvc", 3) == 0) {
511 PcdSet32 (PcdArmPsciMethod
, 1);
512 } else if (PsciMethod
&& AsciiStrnCmp (PsciMethod
, "smc", 3) == 0) {
513 PcdSet32 (PcdArmPsciMethod
, 2);
515 DEBUG ((EFI_D_ERROR
, "%a: Unknown PSCI method \"%a\"\n", __FUNCTION__
,
526 // UEFI takes ownership of the RTC hardware, and exposes its functionality
527 // through the UEFI Runtime Services GetTime, SetTime, etc. This means we
528 // need to disable it in the device tree to prevent the OS from attaching its
529 // device driver as well.
531 if ((RtcNode
!= -1) &&
532 fdt_setprop_string (DeviceTreeBase
, RtcNode
, "status",
534 DEBUG ((EFI_D_WARN
, "Failed to set PL031 status to 'disabled'\n"));