1 /** @file NorFlashDxe.h
3 Copyright (c) 2011, ARM Ltd. All rights reserved.<BR>
4 This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution. The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14 #ifndef __NOR_FLASH_DXE_H__
15 #define __NOR_FLASH_DXE_H__
21 #include <Protocol/BlockIo.h>
22 #include <Protocol/FirmwareVolumeBlock.h>
24 #include <Library/DebugLib.h>
25 #include <Library/IoLib.h>
26 #include <Library/NorFlashPlatformLib.h>
27 #include <Library/UefiLib.h>
29 #include <ArmPlatform.h>
31 #define HIGH_16_BITS 0xFFFF0000
32 #define LOW_16_BITS 0x0000FFFF
33 #define LOW_8_BITS 0x000000FF
35 // Device access macros
36 // These are necessary because we use 2 x 16bit parts to make up 32bit data
38 #define FOLD_32BIT_INTO_16BIT(value) ( ( value >> 16 ) | ( value & LOW_16_BITS ) )
40 #define GET_LOW_BYTE(value) ( value & LOW_8_BITS )
41 #define GET_HIGH_BYTE(value) ( GET_LOW_BYTE( value >> 16 ) )
43 // Each command must be sent simultaneously to both chips,
44 // i.e. at the lower 16 bits AND at the higher 16 bits
45 #define CREATE_NOR_ADDRESS(BaseAddr,OffsetAddr) ((BaseAddr) + ((OffsetAddr) << 2))
46 #define CREATE_DUAL_CMD(Cmd) ( ( Cmd << 16) | ( Cmd & LOW_16_BITS) )
47 #define SEND_NOR_COMMAND(BaseAddr,OffsetAddr,Cmd) MmioWrite32 (CREATE_NOR_ADDRESS(BaseAddr,OffsetAddr), CREATE_DUAL_CMD(Cmd))
48 #define GET_NOR_BLOCK_ADDRESS(BaseAddr,Lba,LbaSize)( BaseAddr + (UINTN)((Lba) * LbaSize) )
50 // Status Register Bits
51 #define P30_SR_BIT_WRITE (BIT7 << 16 | BIT7)
52 #define P30_SR_BIT_ERASE_SUSPEND (BIT6 << 16 | BIT6)
53 #define P30_SR_BIT_ERASE (BIT5 << 16 | BIT5)
54 #define P30_SR_BIT_PROGRAM (BIT4 << 16 | BIT4)
55 #define P30_SR_BIT_VPP (BIT3 << 16 | BIT3)
56 #define P30_SR_BIT_PROGRAM_SUSPEND (BIT2 << 16 | BIT2)
57 #define P30_SR_BIT_BLOCK_LOCKED (BIT1 << 16 | BIT1)
58 #define P30_SR_BIT_BEFP (BIT0 << 16 | BIT0)
60 // Device Commands for Intel StrataFlash(R) Embedded Memory (P30) Family
62 // On chip buffer size for buffered programming operations
63 // There are 2 chips, each chip can buffer up to 32 (16-bit)words, and each word is 2 bytes.
64 // Therefore the total size of the buffer is 2 x 32 x 2 = 128 bytes
65 #define P30_MAX_BUFFER_SIZE_IN_BYTES ((UINTN)128)
66 #define P30_MAX_BUFFER_SIZE_IN_WORDS (P30_MAX_BUFFER_SIZE_IN_BYTES/((UINTN)4))
67 #define MAX_BUFFERED_PROG_ITERATIONS 10000000
68 #define BOUNDARY_OF_32_WORDS 0x7F
71 #define P30_CFI_ADDR_QUERY_UNIQUE_QRY 0x10
72 #define P30_CFI_ADDR_VENDOR_ID 0x13
75 #define CFI_QRY 0x00595251
78 #define P30_CMD_READ_DEVICE_ID 0x0090
79 #define P30_CMD_READ_STATUS_REGISTER 0x0070
80 #define P30_CMD_CLEAR_STATUS_REGISTER 0x0050
81 #define P30_CMD_READ_ARRAY 0x00FF
82 #define P30_CMD_READ_CFI_QUERY 0x0098
85 #define P30_CMD_WORD_PROGRAM_SETUP 0x0040
86 #define P30_CMD_ALTERNATE_WORD_PROGRAM_SETUP 0x0010
87 #define P30_CMD_BUFFERED_PROGRAM_SETUP 0x00E8
88 #define P30_CMD_BUFFERED_PROGRAM_CONFIRM 0x00D0
89 #define P30_CMD_BEFP_SETUP 0x0080
90 #define P30_CMD_BEFP_CONFIRM 0x00D0
93 #define P30_CMD_BLOCK_ERASE_SETUP 0x0020
94 #define P30_CMD_BLOCK_ERASE_CONFIRM 0x00D0
97 #define P30_CMD_PROGRAM_OR_ERASE_SUSPEND 0x00B0
98 #define P30_CMD_SUSPEND_RESUME 0x00D0
100 // BLOCK LOCKING / UNLOCKING Commands
101 #define P30_CMD_LOCK_BLOCK_SETUP 0x0060
102 #define P30_CMD_LOCK_BLOCK 0x0001
103 #define P30_CMD_UNLOCK_BLOCK 0x00D0
104 #define P30_CMD_LOCK_DOWN_BLOCK 0x002F
106 // PROTECTION Commands
107 #define P30_CMD_PROGRAM_PROTECTION_REGISTER_SETUP 0x00C0
109 // CONFIGURATION Commands
110 #define P30_CMD_READ_CONFIGURATION_REGISTER_SETUP 0x0060
111 #define P30_CMD_READ_CONFIGURATION_REGISTER 0x0003
113 #define NOR_FLASH_SIGNATURE SIGNATURE_32('n', 'o', 'r', '0')
114 #define INSTANCE_FROM_FVB_THIS(a) CR(a, NOR_FLASH_INSTANCE, FvbProtocol, NOR_FLASH_SIGNATURE)
115 #define INSTANCE_FROM_BLKIO_THIS(a) CR(a, NOR_FLASH_INSTANCE, BlockIoProtocol, NOR_FLASH_SIGNATURE)
117 typedef struct _NOR_FLASH_INSTANCE NOR_FLASH_INSTANCE
;
119 typedef EFI_STATUS (*NOR_FLASH_INITIALIZE
) (NOR_FLASH_INSTANCE
* Instance
);
122 VENDOR_DEVICE_PATH Vendor
;
123 EFI_DEVICE_PATH_PROTOCOL End
;
124 } NOR_FLASH_DEVICE_PATH
;
126 struct _NOR_FLASH_INSTANCE
{
131 NOR_FLASH_INITIALIZE Initialize
;
137 EFI_BLOCK_IO_PROTOCOL BlockIoProtocol
;
138 EFI_BLOCK_IO_MEDIA Media
;
141 EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL FvbProtocol
;
143 NOR_FLASH_DEVICE_PATH DevicePath
;
148 NorFlashGetDriverName (
149 IN EFI_COMPONENT_NAME_PROTOCOL
*This
,
151 OUT CHAR16
**DriverName
156 NorFlashGetControllerName (
157 IN EFI_COMPONENT_NAME_PROTOCOL
*This
,
158 IN EFI_HANDLE ControllerHandle
,
159 IN EFI_HANDLE ChildHandle OPTIONAL
,
161 OUT CHAR16
**ControllerName
166 NorFlashBlkIoInitialize (
167 IN NOR_FLASH_INSTANCE
* Instance
171 NorFlashReadCfiData (
172 IN UINTN BaseAddress
,
174 IN UINT32 NumberOfBytes
,
179 NorFlashWriteBuffer (
180 IN UINTN TargetAddress
,
181 IN UINTN BufferSizeInBytes
,
187 // BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.Reset
191 NorFlashBlockIoReset (
192 IN EFI_BLOCK_IO_PROTOCOL
*This
,
193 IN BOOLEAN ExtendedVerification
197 // BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.ReadBlocks
201 NorFlashBlockIoReadBlocks (
202 IN EFI_BLOCK_IO_PROTOCOL
*This
,
205 IN UINTN BufferSizeInBytes
,
210 // BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.WriteBlocks
214 NorFlashBlockIoWriteBlocks (
215 IN EFI_BLOCK_IO_PROTOCOL
*This
,
218 IN UINTN BufferSizeInBytes
,
223 // BlockIO Protocol function EFI_BLOCK_IO_PROTOCOL.FlushBlocks
227 NorFlashBlockIoFlushBlocks (
228 IN EFI_BLOCK_IO_PROTOCOL
*This
238 NorFlashFvbInitialize (
239 IN NOR_FLASH_INSTANCE
* Instance
245 IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL
*This
,
246 OUT EFI_FVB_ATTRIBUTES_2
*Attributes
252 IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL
*This
,
253 IN OUT EFI_FVB_ATTRIBUTES_2
*Attributes
258 FvbGetPhysicalAddress(
259 IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL
*This
,
260 OUT EFI_PHYSICAL_ADDRESS
*Address
266 IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL
*This
,
268 OUT UINTN
*BlockSize
,
269 OUT UINTN
*NumberOfBlocks
275 IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL
*This
,
278 IN OUT UINTN
*NumBytes
,
285 IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL
*This
,
288 IN OUT UINTN
*NumBytes
,
295 IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL
*This
,
304 NorFlashUnlockAndEraseSingleBlock(
305 IN UINTN BlockAddress
309 NorFlashWriteSingleBlock (
310 IN UINTN DeviceBaseAddress
,
312 IN UINT32
*pDataBuffer
,
313 IN UINT32 BlockSizeInWords
317 NorFlashWriteBlocks (
318 IN NOR_FLASH_INSTANCE
*Instance
,
320 IN UINTN BufferSizeInBytes
,
326 IN NOR_FLASH_INSTANCE
*Instance
,
328 IN UINTN BufferSizeInBytes
,
334 IN NOR_FLASH_INSTANCE
*Instance
337 #endif /* __NOR_FLASH_DXE_H__ */